IC Design AI/ML Silicon Debug & Yield Engineer

Role Summary

This position involves owning the end-to-end silicon diagnostic pipeline, focusing on utilizing AI and ML methodologies to analyze large volumes of scan failure data and drive yield improvements in semiconductor manufacturing.

Experience Level

The position requires a high level of expertise in ASIC design engineering with at least 8 years of related experience for those with a Bachelor's degree, or 6 years for those with a Master's. A substantial background in Silicon Debug, DFT, or Yield Engineering is necessary.

Responsibilities

Key responsibilities include:

• Developing and deploying ML models for automated classification of scan failures.
• Integrating data to predict yield excursions using high-dimensional data.
• Conducting holistic yield analysis by investigating design marginalities and manufacturing variations.
• Evaluating and implementing AI-based EDA tools for systematic defect identification.
• Facilitating cross-functional communication between manufacturing, design, and test teams.

Requirements

The ideal candidate will possess:

• Deep understanding of ASIC design components.
• Proficiency in Python, especially with libraries like Pandas, Scikit-Learn, and PyTorch/TensorFlow.
• Experience with yield management systems and semiconductor manufacturing processes.
• Ability to analyze and interpret complex data sets effectively.
• Understanding of semiconductor effects such as IR drop and crosstalk.

Education Requirements

A Bachelor's degree in a relevant field plus 8 years of experience, or a Master's degree with 6 years of experience is required.