HPC SoC Timing Design Engineer/Leader

Job Title

HPC SoC Timing Design Engineer/Leader

Role Summary

Lead or senior individual-contributor role responsible for timing design and timing-closure activities for high-performance automotive SoCs (process node: 3nm). The role works with global design centers and EDA vendors to deliver static timing analysis, timing constraints and logic synthesis for large, complex SoC designs.

The position involves both hands-on timing engineering and leadership of technical tasks, collaborating with teams in Vietnam and India and cross-functional product groups.

Experience Level

Senior — requires substantial experience. The posting specifies over 8 years of timing design experience and expects strong leadership capability.

Responsibilities

Primary responsibilities include technical execution of timing closure and coordination with cross-site teams and EDA partners.

• Perform Static Timing Analysis (STA) using EDA vendor tools to verify and close timing for SoC designs.
• Develop, debug and maintain timing constraints using EDA vendor tools and Renesas internal tools.
• Run and validate logic synthesis flows with vendor tools to meet timing and area targets.
• Develop and improve timing-design technology and development flows for large-scale SoCs.
• Coordinate timing activities with overseas design centers and EDA vendors; ensure consistent methodologies across sites.
• Provide technical leadership, mentoring, and reviews for timing engineers on the team.
• Contribute to product development cycles and support delivery for automotive SoC programs.

Requirements

Key qualifications and skills. Must-haves are listed first; nice-to-haves follow.

• Must-have: Over 8 years of timing design experience, including STA and timing-constraint debugging.
• Must-have: Practical experience using EDA vendor tools for STA, timing constraints, and logic synthesis.
• Must-have: Communicative English and communicative Japanese for cross-site collaboration.
• Must-have: Proven ability to lead technical work and propose effective solutions.
• Nice-to-have: Experience with hardware description languages (e.g., Verilog-HDL).
• Nice-to-have: Prior experience working across global design centers and with EDA vendor partners.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.