High-Speed IO Analog/Mixed-Signal Architect / Design Engineer

Job Title

High-Speed IO Analog/Mixed-Signal Architect / Design Engineer

Role Summary

Senior analog/mixed-signal IP architect responsible for the design and delivery of high-speed IO, memory PHYs (LPDDRx, gDDRx, HBMx) and die-to-die PHY IP. Member of AMD's AMS IP design team, collaborating with system/platform and SoC architects to translate system-level requirements into circuit- and block-level specifications.

Location: San Jose, CA with a hybrid work arrangement (role is based in California).

Experience Level

Senior technical role. The posting expects an experienced technical leader with prior responsibility for architecture, sign-off and delivery of AMS IP; specific years of experience are not stated.

Responsibilities

Primary responsibilities include architecture, specification, verification, and production delivery of AMS IP.

• Architect and design high-speed IO/DDR/die-to-die (d2d)/SerDes analog and mixed-signal circuits.
• Define, review and sign off on AMS IP top-level architecture and component/circuit specifications.
• Translate system-level specs into AMS block and circuit-level requirements in collaboration with system/platform and SoC architects.
• Author AMS block architecture and circuit technical specifications, pre-silicon verification plans, and post-silicon characterization/validation test plans.
• Supervise pre-silicon layout, post-silicon characterization and debug; support product bring-up and sign-off on test plans and characterization reports.
• Work cross-functionally with project managers, IC designers and physical designers to meet schedule and technical goals.

Requirements

Technical must-haves for successful candidates, plus relevant preferences.

• Must-have: Proven track record leading AMS IP architecture, taking designs to production, and supervising pre- and post-silicon activities.
• Must-have: Hands-on experience with multi-Gbps serial interfaces (e.g. PCIe, USB), high-bandwidth memory PHY/IOs (LPDDR, HBM, gDDR) and die-to-die/chip-to-chip links.
• Must-have: Deep knowledge of mixed-signal circuit architecture for receiver/transmitter and PLL/DLL/clocking; familiarity with mismatch mitigation, linearity, stability, low-noise and low-power techniques.
• Must-have: Experience designing mixed-signal circuit blocks such as DLLs, phase interpolators, clock distribution, bandgap/biasing, LDOs, amplifiers, comparators, CDR and duty-cycle correction.
• Must-have: Strong understanding of high-speed IO signaling topologies, link budget analysis, jitter/SNR metrics and system-silicon co-optimization for PPA trade-offs.
• Must-have: Design experience in advanced FinFET CMOS process nodes (examples: 16nm/7nm/3nm) with solid transistor/device fundamentals.
• Must-have: Proficient with AMS design flows and tools (examples: Cadence Virtuoso/schematic capture, Spectre, HSPICE).
• Must-have: Strong analytical, communication and cross-functional collaboration skills; able to operate with minimal supervision and lead technical reviews.
• Nice-to-have: Low-power design techniques for high-speed/custom digital circuits (CMOS/CML) and transistor-level timing sign-off experience.
• Other: This role is not eligible for visa sponsorship; candidates must be authorized to work in the United States (California).

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering or a closely related field, or equivalent practical experience.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.