High Performance DSP core Implementation (Synthesis) Staff Engineer

Job Title

High Performance DSP core Implementation (Synthesis) Staff Engineer

Role Summary

Join the ASIC/ASICS Engineering team responsible for synthesis and implementation of high-performance DSP cores. The role focuses on physical synthesis, timing closure, low-power implementation and handoff of production-quality netlists in collaboration with design, DFT and PD teams.

Experience Level

Senior-level role. The posting specifies 8+ years of hands-on experience in synthesis and logic equivalence checking (LEC).

Responsibilities

Key responsibilities include synthesis implementation, timing optimization, and delivery of verified netlists.

• Develop and execute physical synthesis flows and methodologies using industry tools.
• Write and validate timing constraints for synthesis and STA; drive timing closure and pipelining for performance optimization.
• Perform timing closure for multi-clock-domain designs and support signoff timing flows.
• Implement low-power techniques and UPF-based flows; apply power-optimization strategies such as clock gating.
• Work with design, DFT and PD teams to deliver netlists, validate timing constraints, and manage ECOs.
• Support formal equivalence checking and maintain quality metrics for delivered netlists.
• Automate flows and tasks using scripting; maintain regression and version-control practices.

Requirements

Must-have technical skills and experience for the role.

• Extensive hands-on experience in synthesis and logic equivalence checking (LEC), including signoff flows.
• Strong knowledge of physical synthesis methodologies and tools (e.g., Fusion Compiler, Genus).
• Experience writing timing constraints, static timing analysis (STA), and achieving timing closure.
• Familiarity with MCMM synthesis/optimization and low-power implementation practices.
• Proficiency in scripting (Python, Tcl; Perl experience a plus) to automate flows.
• Proficient in front-end VLSI design: Verilog/VHDL, synthesis QoR optimization, and equivalence checking.
• Experience handling ECOs, collaborating with DFT/PD teams, and using LP signoff tools.
• Familiarity with version control, configuration management, and regression frameworks is a plus.

Education Requirements

Requires a Bachelor's degree in Science, Engineering or related field with 4+ years of relevant ASIC experience; or a Master’s degree with 3+ years; or a PhD with 2+ years. Equivalent practical experience in ASIC design, verification, validation, integration, or related work is accepted per the posting.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.