High Performance DSP Core Implementation (Synthesis) Senior Staff Engineer
QualcommJob Title
High Performance DSP Core Implementation (Synthesis) Senior Staff Engineer
Role Summary
Lead synthesis and implementation efforts for high-performance DSP cores within the ASICS Engineering team. Responsible for physical synthesis, timing closure, low-power implementation, netlist delivery, and coordination with design, DFT and physical-design teams.
Experience Level
Senior-level role; typically requires extensive hands-on experience in synthesis and equivalence checking. Candidates are expected to have deep domain experience (see Education Requirements for minimum experience tied to degree).
Responsibilities
Primary responsibilities include:
- Develop and apply physical synthesis methodologies using industry-standard tools.
- Write timing constraints, perform STA, and drive timing closure across multi-clock-domain designs.
- Optimize performance with pipelining and QoR techniques; implement MCMM synthesis where needed.
- Implement low-power strategies using UPF and clock-gating techniques.
- Produce and validate netlists; coordinate with design, DFT, and PD teams for delivery.
- Manage ECOs, perform formal equivalence checks, and maintain quality metrics.
- Automate flows and scripts using Python, Tcl (and Perl where applicable).
Requirements
Must-have technical skills and experience:
- Extensive hands-on experience in synthesis and LEC (equivalence checking); source lists 12+ years of relevant experience.
- Proficiency in Python and Tcl; familiarity with Perl is a plus.
- Experience with synthesis tools such as Fusion Compiler and Genus; familiarity with LP signoff tools.
- Strong front-end VLSI skills: Verilog/VHDL, synthesis, QoR optimization.
- Proven experience writing timing constraints, performing STA, and achieving timing closure on complex designs.
- Knowledge of low-power implementation techniques and UPF flows.
- Ability to work independently with cross-functional teams to deliver high-quality netlists and address ECOs.
- Familiarity with version control, configuration management, and regression practices is preferred.
Education Requirements
Bachelor's degree in Science, Engineering, or related field plus 6+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or related field plus 5+ years; OR PhD in Science, Engineering, or related field plus 4+ years.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
