High Performance DSP Core Implementation (Synthesis) Senior Lead Engineer
QualcommJob Title
High Performance DSP Core Implementation (Synthesis) Senior Lead Engineer
Role Summary
Lead synthesis and implementation activities for high-performance DSP cores within the ASIC/SoC implementation team. The role focuses on physical synthesis, timing closure, low-power implementation, equivalence checking and delivering high-quality netlists for tape-out.
Experience Level
Senior-level. The posting specifies 5–8 years of hands-on experience in synthesis and LEC and expects demonstrated senior engineering ownership of synthesis, timing closure, and implementation flows.
Responsibilities
Primary responsibilities center on synthesis, timing closure and collaboration with cross-functional teams to deliver production-quality netlists.
- Define and execute physical synthesis and optimization flows using industry tools.
- Write and validate timing constraints for synthesis and STA; drive timing closure across multiple clock domains.
- Implement low-power techniques and UPF-driven flows; apply clock gating and other power optimizations.
- Work with design, DFT and PD teams to deliver and validate netlists; support ECOs and iterative fixes.
- Perform equivalence checking and support formal verification related to synthesis changes.
- Automate synthesis and signoff flows using scripting and create repeatable regression flows.
Requirements
Must-have technical skills and tools experience for this role.
- Strong understanding of physical synthesis methodologies and QoR optimization.
- Experience writing timing constraints and achieving timing closure for multi-clock designs.
- Proficiency with synthesis tools such as Fusion Compiler or Genus.
- Hands-on experience with LEC and low-power (LP) signoff tools.
- Proficient in scripting (Python, Tcl); Perl experience is a plus.
- Experienced in front-end design: Verilog/VHDL, synthesis, and equivalence checking workflows.
- Familiarity with UPF-based low-power implementation and common power-optimization techniques (clock gating).
- Ability to manage ECOs, validate timing constraints, and collaborate across teams to meet delivery targets.
- Nice-to-have: experience with version control, configuration management, regression frameworks, and formal verification integration.
Education Requirements
Bachelor's degree in Science, Engineering or a related field with 3+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering or related field with 2+ years of such experience; OR PhD in Science, Engineering or related field with 1+ year of such experience. (These degree-and-experience combinations are listed as the minimum qualifications.)
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
