High Performance DSP Core Implementation (Synthesis) Senior Engineer
QualcommJob Title
High Performance DSP Core Implementation (Synthesis) Senior Engineer
Role Summary
Engineer in the ASICS/Hardware Engineering group responsible for synthesis and implementation of high-performance DSP cores and related IP for SoC products. Deliver synthesis netlists, meet timing and power targets, and collaborate with design, DFT and physical design teams.
Work focuses on timing closure, low-power implementation, and quality signoff for multi-clock-domain designs.
Experience Level
Senior - the posting specifies 3+ years of hands-on experience in synthesis and equivalence checking (LEC); minimum qualifications also list degree-based experience alternatives (see Education Requirements).
Responsibilities
Key responsibilities include synthesis, timing closure, and collaboration across implementation teams.
- Implement physical synthesis and apply synthesis methodologies using industry-standard tools.
- Write and validate timing constraints for synthesis and STA; drive timing closure and pipelining for performance optimization.
- Manage timing closure across multi-clock-domain designs.
- Apply MCMM synthesis and optimization techniques for multi-clock designs.
- Implement low-power design techniques and flows using UPF and clock-gating.
- Develop and maintain scripts (Python/Perl/Tcl) to automate flows and QoR tuning.
- Coordinate with design, DFT and PD teams for netlist delivery and constraint validation; handle ECOs and formal verification tasks.
Requirements
Must-have technical skills and practical experience; listed as concise must-have vs nice-to-have.
- Must-have: Hands-on experience in synthesis and LEC; proficiency with synthesis tools such as Fusion Compiler or Genus.
- In-depth knowledge of timing closure, STA, pipelining, and QoR optimization for performance-driven designs.
- Experience with multi-clock-domain timing closure and MCMM optimization.
- Familiarity with low-power implementation flows (UPF) and power-optimization techniques such as clock-gating.
- Proficiency in scripting (Python, Tcl, or Perl) for automation and flow development.
- Proficient in front-end RTL (Verilog/VHDL), synthesis flows, QoR optimization, and equivalence checking practices.
- Ability to manage ECOs and work with formal verification and cross-functional teams to maintain design quality.
- Nice-to-have: Familiarity with version control, configuration management, and regression practices.
Education Requirements
Posting specifies a Bachelor's degree in Science, Engineering, or related field (with 2+ years ASIC experience) OR a Master's degree in Science, Engineering, or related field (with 1+ year ASIC experience) OR a PhD in Science, Engineering, or related field. The posting provides degree-based experience alternatives rather than a single fixed degree requirement.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
