HIG HBM Staff Circuit Verification Engineer

Job Title

HIG HBM Staff Circuit Verification Engineer

Role Summary

Responsible for circuit-level verification and debugging of HBM memory designs. Work includes schematic analysis, SPICE and gate-level simulations, SDF back-annotation, timing analysis, and collaboration with design teams to diagnose and fix circuit- and timing-related issues.

Position sits within the engineering verification team supporting HBM (High Bandwidth Memory) IP development and tapeout readiness at Micron's Hyderabad site.

Experience Level

Senior — typically 5+ years of relevant circuit verification, simulation, and debug experience.

Responsibilities

Primary responsibilities include circuit- and gate-level verification, simulation correlation, and problem resolution:

• Develop and read building-block and memory schematics; perform DC and transient circuit simulations using SPICE.
• Analyze circuit behavior from schematics and simulation results; perform spice correlation with gate-level results.
• Characterize circuits and work with timing libraries, timing files/formats, and timing arcs.
• Run netlist simulations including Verilog MOS switch-level models with zero/unit/path delays.
• Perform gate-level simulations with SDF back-annotation and debug SDF annotation issues; ensure sufficient annotation coverage.
• Address latch-based design timing requirements and debug related failures.
• Root-cause gate-level simulation failures to transistor or gate-level issues and implement fixes or what-if analyses to verify solutions.
• Specify expected design behavior using SystemVerilog Assertions and communicate technical findings to design peers in verbal and written form.

Requirements

Must-have technical skills and experience:

• Hands-on experience with SPICE circuit simulation (DC/transient) and circuit schematic analysis.
• Experience with gate-level simulation, SDF back-annotation, and debugging annotation or simulation failures.
• Familiarity with static timing analysis and timing library concepts.
• Experience with Verilog MOS switch-level models and netlist simulations.
• Experience debugging latch-based timing issues and performing root-cause analysis to the gate/transistor level.
• Ability to write and use SystemVerilog Assertions; strong technical communication skills.

Nice-to-have:

• Familiarity with UVM.

Education Requirements

BE (Bachelor of Engineering) or MTech (Master of Technology). No specific field of study listed.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.