Head of Test Development Engineering
EthernoviaJob Title
Head of Test Development Engineering
Role Summary
Lead semiconductor test development and delivery from NPI to high-volume manufacturing for automotive-grade Ethernet switch and PHY products. Own test architecture, hardware, infrastructure, labs and vendor relationships to ensure production-ready, reliable test flows.
Cross-functional role based in San Jose, CA, collaborating with Architecture, Design, DFT, Security, SW/FW, System, Product and Quality & Reliability teams.
Experience Level
Senior — requires 12+ years of experience in fabless semiconductor operations and test development.
Responsibilities
Primary responsibilities include end-to-end ownership of test strategy and delivery:
- Define and own ATE and SLT test architecture from pre-silicon through post-silicon and HVM.
- Develop and deliver manufacturing test programs and test boards ensuring SI/PI and test-time targets are met at scale.
- Design and validate wafer and final test flows, multi-site parallel testing, and system-level tests.
- Engage early with Architecture, DFT, System, SW and Security to ensure testability and debugability.
- Manage test labs, OSAT relationships, and procurement/qualification of tester, prober, probe cards, load boards, sockets and handlers.
- Lead debug, characterization and automation for high-speed IO, SerDes, PHY and switch products.
- Define DFT/DFM/DFD requirements and support production readiness, safe launch and PPAP activities.
Requirements
Must-have technical skills and experience:
- 12+ years in fabless semiconductor test development for complex, high-performance SoCs or networking ICs.
- Deep experience with ATE platforms (93K) and Smartest; test method libraries and test program development.
- Expertise in iJTAG, scan (SSN), MBIST, memory and sensor test, SerDes and high-speed IO characterization.
- Proven SLT experience including bare-metal/functional testing, DVFS and benchmark testing, and multi-site handler automation.
- Strong SI/PI skills for tester, probe and load board design and test implementation.
- Experience defining DFT/DFM/DFD for Ethernet PHY and switch products and using scan/memory dumps for debug.
- Familiarity with automotive manufacturing and quality processes (IATF 16949, ISO 26262, Safe launch, PPAP).
- Vendor management experience with OSATs and test-equipment suppliers.
Nice-to-have:
- Experience delivering high-speed SerDes products to Tier-1 automotive OEMs.
- Simulation, pattern generation and pattern conversion experience.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering or a related technical field (as stated in the posting).
About the Company
Company: Ethernovia
Develops advanced automotive communication semiconductors and systems, focusing on digital SoC design and verification for networking, video, DSP and related IP. Startup-stage employer offering pre-IPO stock options and benefits.
