HBM SoC RTL Design Engineer

Job Title

HBM SoC RTL Design Engineer

Role Summary

As a SoC Design Engineer within the Heterogeneous Integration Group (HIG), you will implement RTL for HBM logic die and integrate internal and third-party IP. Work across architecture, verification, physical design, firmware, and product teams to deliver robust, high-performance SoC solutions that meet power, performance, area, and schedule targets. Integrate AI-driven tools and AI-enabled workflows into the team's methodologies.

Experience Level

Mid-level role. See Education Requirements for the explicit years-of-experience expectation.

Responsibilities

Primary responsibilities include:

• Design and implement RTL for SoC-level blocks and subsystems targeting HBM logic die.
• Integrate internal and third-party IP (controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Translate architectural and micro-architectural specifications into high-quality RTL implementations in collaboration with SoC architects.
• Participate in SoC-level integration activities: clocking, reset, power intent, and configuration infrastructure.
• Support pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.

Requirements

Must-have technical skills and experience:

• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL-to-GDS flow, including synthesis and static timing analysis.
• Familiarity with EDA tool flows from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (Python, TCL, Perl, or shell scripting).
• Strong debugging and root-cause analysis skills for pre- and post-silicon validation.

Nice-to-have:

• Experience with HBM, DRAM, or memory-centric SoC designs.
• Familiarity with high-speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (Palladium, Veloce, Zebu).
• Familiarity with or willingness to learn Agentic AI and AI-enabled workflows.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. The posting specifies a minimum of 6 years of related experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.