HBM SoC Physical Design Engineer

Job Title

HBM SoC Physical Design Engineer

Role Summary

Hands-on SoC physical design engineer in the Heterogeneous Integration Group responsible for implementing advanced HBM SoC logic/base die designs from netlist to GDSII. Collaborates with RTL, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to meet performance, power, area (PPA) targets and produce robust signoff collateral for tape-out.

Opportunity to own physical implementation of blocks or top-level integration across multiple product generations and support tape-out execution and post-silicon debug.

Experience Level

Senior-level. Minimum ~10 years of related experience is preferred.

Responsibilities

Primary responsibilities include physical implementation, timing closure, signoff, and cross-team integration.

• Own physical implementation for SoC blocks and/or top-level: floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner scenarios; collaborate with RTL, architecture, and STA/signoff teams.
• Integrate and implement complex IP (controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with a focus on timing and power integrity.
• Perform and/or coordinate physical signoff activities: DRC/LVS, IR drop/EM analysis, parasitic extraction awareness, and timing signoff.
• Partner with DFT teams to ensure scan/MBIST requirements are physically realizable without compromising PPA or schedule.
• Work with packaging, assembly, test, probe, and manufacturing to ensure manufacturability and quality.
• Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and methodology development.

Requirements

Must-have and nice-to-have qualifications summarized below.

Must-have:

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced process nodes and complex designs.
• Proficiency with industry EDA tools (for example, Cadence Innovus/Tempus; Synopsys ICC2/PrimeTime; Siemens Calibre or equivalents).
• Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
• Experience with power intent and power delivery considerations (UPF/CPF concepts, power grid planning, power gating impacts).
• Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction, and signoff handoff quality.

Nice-to-have:

• Experience with HBM or DRAM-adjacent SoC designs or memory-subsystem-heavy SoCs.
• Proven ability to mentor and develop early-career engineers.

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field is preferred; equivalent practical experience is acceptable.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.