HBM SoC Physical Design Engineer

Job Title

HBM SoC Physical Design Engineer

Role Summary

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will implement advanced HBM SoC logic/base die designs from netlist to GDSII and deliver PPA and signoff collateral for tape-out. The role is hands-on and involves ownership of blocks or top-level integration across multiple product generations.

You will work cross-functionally with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams, and contribute to integrating AI-driven tools and automation into physical design workflows.

Experience Level

Mid-level (typically 3+ years of related SoC physical design experience).

Responsibilities

Primary responsibilities include:

• Own physical implementation for SoC blocks and/or top-level: floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner scenarios; collaborate with RTL, architecture, and STA/signoff teams.
• Integrate complex IP (controllers, NOC, interfaces, MBIST/DFT logic, PHY-adjacent logic) with focus on physical integration, timing, and power integrity.
• Perform or coordinate physical signoff: DRC/LVS, IR drop/EM analysis, parasitic extraction awareness, and timing signoff handoffs.
• Partner with DFT to ensure scan/MBIST requirements are physically realizable without compromising PPA or schedule.
• Collaborate with packaging, assembly, test, probe, and manufacturing teams to ensure manufacturability and quality.
• Support tape-out execution (checklists, ECO flows, signoff reviews) and assist post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting, automation, and methodology improvements.

Requirements

Must-have technical skills and experience:

• Proven SoC physical design implementation experience from netlist to GDSII on advanced nodes and complex designs.
• Proficiency with industry EDA tools (examples: Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalents).
• Solid understanding of static timing analysis fundamentals, clocking, SDC constraints, and common closure techniques (buffering, path shaping, useful skew, etc.).
• Experience with power intent and power delivery considerations (UPF/CPF concepts, power grid planning, power gating implications).
• Familiarity with physical verification and signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
• Ability to support tape-out checklists, ECO flows, and signoff reviews.
• Nice-to-have: experience with HBM/DRAM-adjacent SoC designs, mentoring junior engineers, and familiarity or willingness to learn agentic AI tools for workflow automation.

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field preferred.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.