HBM IO Architecture, Principal Engineer

Job Title

HBM IO Architecture, Principal Engineer

Role Summary

Principal engineer responsible for architecture, design, optimization and verification of PHY circuits on the interface die for next-generation High Bandwidth Memory (HBM) products. The role sits in a multi-functional High-Performance Integrated Group working with design engineering, product engineering, process and package teams to deliver industry-leading HBM solutions.

Experience Level

Senior — requires significant hands-on experience. The posting specifies 5+ years of technical experience in IO interfaces and IO circuit design.

Responsibilities

Core responsibilities include IO architecture exploration, PHY circuit development, cross-functional collaboration, and verification/optimization to meet performance, power, cost and quality targets.

• Explore and evaluate new IO architectures for future HBM products; perform technical feasibility analyses and make recommendations.
• Design, develop and optimize HBM PHY circuits for the interface die; consider signal integrity, layout optimization and timing budget closure.
• Correlate silicon measurements with simulation results to drive circuit-level design improvements.
• Collaborate with memory, interface, product, process integration and transistor modeling teams to meet speed, power, cost and quality goals.
• Perform circuit verification activities including layout verification and parasitic extraction; work toward IP-level verification closure.
• Contribute to cross-group standardization, provide technical guidance and solicit mentorship from standards, CAD, modeling and verification groups.

Requirements

Required and preferred technical skills for successful performance in the role.

• Must-have: Strong analog and digital IO circuit design and simulation experience (including single-ended Rx, buffers, IO, Tx, SerDes, equalizers, DCC, phase interpolators).
• Must-have: Hands-on experience with FinFET device characteristics and practical circuit design using advanced process nodes.
• Must-have: Experience with circuit verification, layout verification and parasitic extraction.
• Must-have: Familiarity with off-chip protocols such as HBM, UCIe or other DRAM interfaces.
• Nice-to-have: IP-level verification experience, strong RTL debugging skills, and front-end implementation experience (synthesis, STA, equivalence).
• Nice-to-have: Scripting skills (Python, Tcl, Perl, shell, ACE) for automation and analysis.
• Nice-to-have: Understanding of device physics, CMOS processing techniques and BSIM transistor models; past circuit debug through product engineering is a plus.
• Excellent analytical and communication skills; ability to convey complex technical concepts in writing and verbally.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) specified. The posting also specifies 5+ years of proven experience in IO interfaces and related circuit work. No other degrees, fields of study, certifications, or explicit "equivalent experience" language were provided.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.