HBM Design Engineering Lead (MTS/SMTS/DMTS)

Job Title

HBM Design Engineering Lead (MTS/SMTS/DMTS)

Role Summary

Senior technical contributor and project lead responsible for delivering High Bandwidth Memory (HBM) design blocks and subsystems from architecture through silicon bring-up and post-silicon support. The role partners across design, process, packaging, and product teams to deliver reliable, high-performance memory solutions for AI and high-performance computing workloads.

Based in Richardson, TX, the position mentors engineers, defines technical strategy, and drives execution for HBM programs.

Experience Level

Senior — requires extensive industry experience (see requirements). Positioned as a technical leader and mentor.

Responsibilities

Key responsibilities include end-to-end delivery, cross-functional leadership, and technical problem resolution for HBM programs.

• Own and deliver HBM design blocks and subsystems from architecture through schematic, implementation, verification, tape-out, and post-silicon debug.
• Balance performance, power, reliability, yield, and manufacturability trade-offs to produce robust, high-performance designs.
• Lead root-cause analysis and resolution of pre-silicon and post-silicon issues across circuit design, architecture, process integration, and packaging interactions.
• Serve as technical project lead for HBM programs, coordinating across architecture, layout, verification, validation, process integration, packaging, test, and product teams.
• Define and communicate technical strategy, priorities, and execution plans; identify risks, dependencies, and schedule impacts.
• Research and influence next-generation HBM architectures for AI, machine learning, and HPC workloads.
• Mentor engineers through design reviews, architectural guidance, and hands-on problem solving; improve design methods and execution discipline.

Requirements

Must-have and preferred technical skills and experience.

• Must-have: 15+ years of experience in DRAM, HBM, advanced memory, SoC, or ASIC design roles; proven record delivering complex designs from architecture through silicon bring-up and post-silicon debug.
• Must-have: Strong expertise in DRAM operation and JEDEC standards, preferably including HBM product families.
• Must-have: Extensive experience with CMOS circuit design, transistor-level design, and semiconductor device physics.
• Must-have: Demonstrated technical project leadership coordinating multidisciplinary engineering teams.
• Nice-to-have: Digital design using RTL methodologies (e.g., Verilog) and experience with analog modeling/simulation tools (FastSpice, HSPICE, or similar).
• Nice-to-have: Deep expertise in DRAM memory array design, high-speed clocking/interface design, logic/custom circuit design, or power delivery optimization.
• Nice-to-have: Exposure to 2.5D/3D packaging technologies (TSVs, hybrid bonding, interposers).
• Nice-to-have: Strong communication skills for explaining complex technical concepts to engineers, leaders, and customers.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.