HBM 3D Power Delivery Network (PDN) Engineer

Job Title

HBM 3D Power Delivery Network (PDN) Engineer

Role Summary

Hands-on PDN engineer in the Heterogeneous Integration Group (HIG) responsible for designing, analyzing, and optimizing power delivery networks for HBM and related high-performance memory products. Works across architecture, physical design, packaging, and product engineering to deliver manufacturable PDN solutions that meet performance, power integrity and reliability targets.

Experience Level

Senior — typically 10+ years of relevant PDN, EM/IR, and SoC/ASIC experience (the posting lists a minimum of 10 years preferred).

Responsibilities

Design, analyze, and close power-delivery and power-integrity requirements across die, package, and system for HBM/3DIC products.

• Design SoC-level and HBM-cube-level power grid architectures, routing strategies, and decoupling schemes.
• Perform EM/IR analysis and optimization with industry tools to ensure power integrity under dynamic workloads.
• Collaborate with floorplanning, placement, and routing teams to enable efficient PDN implementation in physical designs.
• Drive power-integrity closure across multi-mode, multi-corner scenarios; mitigate droop, noise, and electromigration risks.
• Co-optimize die-package-system PDN interactions, including bump/pad assignment and current distribution.
• Develop and validate power models (activity-based current profiles, transient analysis) and support silicon correlation.
• Support signoff activities (EM, IR, reliability) and debug PDN issues pre- and post-silicon.
• Improve PDN methodologies via automation, scripting, and best-practice development.

Requirements

Must-have technical skills and experience needed to perform the role.

• Proven experience in PDN design and analysis for complex SoCs or high-performance ASICs.
• Proficiency with EM/IR analysis tools (examples: Cadence RedHawk, Ansys Totem, or equivalents).
• Proficiency with SPICE-based simulation tools and 3D PDN modeling.
• Strong understanding of IR drop, electromigration, dynamic voltage droop, and power noise mechanisms.
• Experience with physical design flows and RTL-to-GDSII signoff methodologies; ability to work with floorplanning and routing teams.
• Strong analytical and debugging skills with a record of driving complex issues to closure.

Nice-to-have:

• Experience with HBM, DRAM, or memory-centric SoC designs and 3DIC power-delivery challenges.
• Familiarity with die-package-system co-design and advanced packaging (2.5D/3D integration).
• Experience with transient and vector-based power analysis methodologies and JEDEC memory behavior.
• Proven ability to mentor and develop junior engineers.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.