Hardware Technical Program Manager

Job Title

Hardware Technical Program Manager

Role Summary

Lead and execute an end-to-end silicon program from architecture freeze through RTL, verification, physical implementation, tapeout, bring-up, and production release. Act as the program's operational center: build and defend the schedule, drive critical-path execution, surface risks early, and coordinate tradeoffs across engineering, supply chain, and vendor partners.

Experience Level

Senior — requires 7+ years in semiconductor/hardware engineering or program management, including multiple full SoC/ASIC programs taken through tapeout and silicon bring-up.

Responsibilities

Manage program delivery, cross-functional execution, and risk/decision processes for silicon development.

• Own the silicon schedule from architecture freeze through tapeout, bring-up, and production; maintain single source of truth for status and decisions.
• Drive weekly execution cadence: program reviews, design reviews, tapeout readiness, and status reporting.
• Coordinate handoffs across architecture, RTL, verification/emulation, DFT, physical design, IP, package, and software teams.
• Manage dependencies: IP delivery, PDK/library releases, EDA versions, emulation capacity, and supply-chain timing.
• Execute tapeout checklist and signoff matrix (timing, power, IR/EM, DRC/LVS, DFT coverage, ECO closure, GDS handoff).
• Work with supply chain/logistics on IP acquisition, silicon arrival, ATE/loadboard readiness, lab scheduling, and ECO/respin decisions.
• Surface risks with quantified mitigation options and schedule impact; facilitate PPA, schedule, and scope tradeoffs and document decisions.
• Interface with foundry, OSAT, IP, and EDA partners; support export control/ECCN compliance and escalations.
• Produce executive reports on program status, risks, and decision needs; track resource allocation and NRE/mask/license budgets.

Requirements

Must-have technical program management skills and hands-on familiarity with the chip design flow and program tooling.

• 7+ years in semiconductor/hardware engineering or program management; at least 2 full SoC/ASIC programs taken from concept through tapeout and bring-up.
• Working fluency in chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation.
• Proven ability to build and defend bottoms-up schedules with critical-path analysis and dependency mapping.
• Track record influencing without authority; strong written and verbal communication for both engineering and executive audiences.
• Hands-on with program tooling: Jira, Confluence, MS Project or Smartsheet; familiarity with Synopsys/Cadence/Siemens EDA tools and emulation/FPGA prototyping flows.
• Ability to coordinate external partners (foundry, OSAT, IP vendors) and manage vendor deliverables and escalations.
• Experience managing tapeout signoff criteria and post-silicon bring-up activities.
• Nice-to-have: prior hands-on engineering experience in design, verification, or physical design; experience on advanced FinFET nodes (16/12/7nm+); exposure to packaging, board co-design, EVK programs, or relevant quality/compliance frameworks (automotive/industrial/security).

Education Requirements

B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. or MBA is a plus. Equivalent practical experience accepted where indicated.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.