Hardware - Silicon Validation Team Lead (NPU SoC)

Job Title

Hardware - Silicon Validation Team Lead (NPU SoC)

Role Summary

Lead the silicon validation team responsible for system-level verification and bring-up of NPU SoCs from pre-silicon stages through first-silicon bring-up and product stabilization. The role bridges RTL/DV and firmware/software teams to drive validation methodology, bring-up plans, and system reliability for commercial chips.

Experience Level

Senior — a lead-level role. The posting requires senior/lead experience in SoC or silicon validation; specific years of experience are not stated.

Responsibilities

Lead validation planning and execution across pre- and post-silicon activities, own system bring-up, and coordinate cross-functional debugging and fixes.

• Lead 1st-silicon bring-up for NPU accelerator core, CPU subsystem, NoC, memory subsystems (LPDDR/HBM), and high-speed interfaces; oversee board bring-up and system initialization (boot sequence, clocks, resets).
• Define and execute validation plans and coverage for pre-silicon (emulator, FPGA) and post-silicon environments; develop test firmware and scenario tests.
• Debug system-level HW/SW issues using tools like JTAG and Trace32; identify root causes and propose workarounds; report findings to stakeholders.
• Support performance validation and memory bandwidth optimization for NPU data pipelines.
• Implement test automation and CI/CD integration to improve validation efficiency.
• Build and mentor the validation team; establish and enforce validation methodology and processes.

Requirements

Key must-have skills and domain experience followed by relevant preferred skills.

• Must-have: Leadership experience in silicon/System/SoC validation and planning; demonstrated ability to lead bring-up and validation roadmaps.
• Hands-on experience with SoC/ASIC or complex silicon system validation at a senior/lead level.
• Strong understanding of ARM architecture, AMBA buses (AXI, AHB) and general SoC/computer architecture.
• Embedded programming for hardware control and IP testing: C/C++ and Rust in bare-metal environments.
• Proven validation methodology skills: test planning, bug tracking, and coverage management.
• HW/SW co-debugging skills using debuggers such as JTAG/Trace32 and logical problem-solving for complex system issues.
• Nice-to-have / Preferred: Experience with AI accelerators (NPU/TPU), GPU, or complex multicore SoC bring-up; pre-silicon platforms (Palladium, Zebu, FPGA); expertise in Ethernet, CXL, LPDDR, HBM protocols and controllers.
• Familiarity with Linux kernel/device driver internals, Rust in system software, and scripting for test automation (Python, Tcl, Bash).

Education Requirements

Not specified.

About the Company

Company: FuriosaAI

Headquarters: Seoul, South Korea

FuriosaAI develops high-performance, energy-efficient AI inference hardware and software. Founded in 2017 by semiconductor and AI engineers, the company builds AI-native compute platforms to reduce AI energy and operational costs and operates globally with offices in Korea, Silicon Valley, and an R&D lab in Lisbon.