Hardware Signal/Power Integrity Engineer (On-/Off-Chip)

Job Title

Hardware Signal/Power Integrity Engineer (On-/Off-Chip)

Role Summary

Work on signal and power integrity (SI/PI) for FuriosaAI silicon, package, and board domains to ensure robust high-speed interfaces and power-delivery performance across on-chip, chiplet/3DIC, and board-level subsystems.

Report to the hardware team and collaborate with silicon, package, and board engineering to define SI/PI requirements, perform simulation and measurement correlation, and support lab bring-up and debug.

Experience Level

Senior—typically 7+ years; this role specifies 8+ years of relevant SI/PI experience.

Responsibilities

Key responsibilities include simulation, analysis, methodology development, and cross-team coordination:

• Define SI/PI requirements from IP and system-level specifications.
• Perform SI/PI simulations at EM, circuit, and system levels.
• Develop SI/PI methodologies for advanced packaging (chiplet, 3D-IC, die-to-die, chip-to-chip).
• Analyze and optimize SI/PI across on-chip, package, and PCB domains at the system level.
• Provide design guidance on stack-up, interconnect routing, PDN architecture, decoupling strategy, and component selection.
• Collaborate with silicon, package, and board teams to ensure measurement-simulation correlation and system robustness.
• Support lab debug and board/silicon bring-up when required.
• Work with internal teams and external partners to co-optimize SI/PI solutions.

Requirements

Clear distinction between must-have skills and additional desirable experience.

Must-have:

• 8+ years of component- and system-level SI/PI analysis experience.
• Solid understanding of SI/PI fundamentals and methodologies.
• Hands-on experience with lab instruments such as VNA, TDR, and real-time oscilloscopes.
• Proficient with EDA/EM tools (examples: SIwave, HFSS, ADS, HSPICE, Allegro, RedHawk variants).

Nice-to-have:

• SI/PI analysis and optimization for high-speed digital interfaces (PCIe, DDR, Ethernet, etc.).
• Modeling and analysis of complex 3D structures with EM simulation tools.
• On-chip backend sign-off experience (Static/Dynamic IR, EM) and on-/off-chip PDN modeling and budgeting.
• Experience with jitter/glitch analysis and sign-off methodology, TSV/cross-talk issues, and multi-corner/process derating.
• Experience developing reference clock jitter estimation and on-chip clock sign-off methodologies for 3DICs.

Education Requirements

Required: BS or MS in Electrical Engineering, Physics, or a related technical field. Preferred: PhD in Electrical Engineering, Physics, or a related field.

About the Company

Company: FuriosaAI

Headquarters: Seoul, South Korea

FuriosaAI develops high-performance, energy-efficient AI inference hardware and software. Founded in 2017 by semiconductor and AI engineers, the company builds AI-native compute platforms to reduce AI energy and operational costs and operates globally with offices in Korea, Silicon Valley, and an R&D lab in Lisbon.