Hardware Engineering Manager - RTL Design Verification
BAE SystemsJob Title
Hardware Engineering Manager - RTL Design Verification
Role Summary
Lead a Design Verification (DV) group within BAE Systems Electronic Systems to plan, execute, and improve RTL verification for ASIC and FPGA projects. The manager will influence program execution, mentor DV engineers, and coordinate with multidisciplinary engineering and program management teams.
This role uses a hybrid work format with a mix of onsite and remote work and requires U.S. citizenship and eligibility for a Secret security clearance.
Experience Level
Senior-level. The posting specifies BSE with 10+ years of relevant experience or MSE with 8+ years; experience leading DV teams and managing verification across the full ASIC/FPGA lifecycle is required.
Responsibilities
Manage and grow a DV organization and ensure verification activities meet program technical, schedule, and quality targets.
- Lead and manage a team of Design Verification engineers; hire and staff to meet program needs.
- Define and oversee verification planning, architecture, implementation, and coverage closure.
- Assess and adopt modern verification tools, methodologies, and hardware resources to improve DV capability.
- Coordinate with project engineering and hardware managers to monitor program execution and health via metrics.
- Drive scope management, proposal reviews, and bid approval to align technical baselines with schedule and budget risk targets.
- Serve as design review chair or assessor and ensure appropriate subject-matter experts are engaged.
- Provide coaching, performance management, and career development for team members.
- Support business initiatives and continuous improvement within the engineering discipline.
Requirements
Must-have technical and leadership skills for successful delivery of complex electronic system verification.
- Current Secret security clearance or eligibility to obtain one; U.S. citizenship is required.
- Proven experience as a DV Lead on successful projects and leading DV engineers within multidiscipline teams.
- Hands-on experience across all DV phases: planning, architecture, implementation, testing, and coverage closure.
- Practical experience developing testbenches using SystemVerilog with OVM and/or UVM.
- Experience using EDA tools for design verification and driving activities to closure.
- Strong leadership, problem solving, analytical judgment, and written/verbal communication skills.
- Experience presenting technical information to program teams or customers and strong organizational attention to detail.
- Nice-to-have: active DoD clearance, FPGA/ASIC development experience, DSP, Matlab/Simulink, Perl/Python, VHDL, and product lifecycle management knowledge.
Education Requirements
Electrical engineering degree required: Bachelor of Science in Engineering (BSE) with 10+ years of experience, or Master of Science in Engineering (MSE) with 8+ years of experience.
About the Company
Company: BAE Systems
Headquarters: London, United Kingdom
Global defense, aerospace and security company delivering products and services for air, land and naval forces, advanced electronics, cyber and intelligence solutions, and space and mission systems for government and commercial customers.
