Hardware Engineering Internship 2027

Job Title

Hardware Engineering Internship 2027

Role Summary

Full-time summer internship (10–12 weeks) at Riverlane’s head office in Cambridge, UK. You will work with hardware and software engineers, mathematicians and physicists on a focused project that contributes to quantum error correction (QEC) tooling and FPGA/ASIC-related architectures.

Experience Level

Entry-level internship for current university students (undergraduate, master’s or PhD students) with relevant technical experience.

Responsibilities

Work with engineers to research, design and evaluate hardware-related optimisations and implement practical improvements.

• Investigate and evaluate architectural optimisations with experienced engineers.
• Enhance decoder architecture to improve flexibility and processing speed.
• Explore design approaches and assess space/time trade-offs for functionality, resource use and performance.
• Implement and test prototypes or RTL where applicable and document results.
• Communicate findings via technical discussions, presentations and written documentation.
• Learn FPGA development and quantum error correction concepts relevant to the project.

Requirements

Must-have technical skills, logistical requirements, and behaviours for successful internship performance.

• Proficiency in Python.
• Solid understanding of low-level computer architecture.
• Excellent critical-thinking, problem-solving, and communication skills (written and verbal).
• Ability to take initiative and work effectively in a team.
• Willingness to learn FPGA development, quantum computing and quantum error correction.
• Available to work full-time for 10–12 weeks during the summer vacation period.
• Right to work in the UK for the full duration of the internship (UK student-visa holders must confirm visa terms allow full-time internship).
• Successful candidates must sign an agreement assigning intellectual property produced during the internship to Riverlane.

Nice-to-have:

• Experience with RTL development for FPGA or ASIC systems.
• Familiarity or interest in quantum computing.
• Knowledge of optimisation concepts and performance trade-offs.
• Some networking principles knowledge.
• Experience using version control, testing or debugging tools.

Education Requirements

Must be a current student at the time of application: in the second or later year of a Bachelor’s degree, partway through a Master’s degree, or partway through a PhD. Studying Computer Science, Electronic Engineering, Physics, Mathematics or a related technical subject.

About the Company

Company: Riverlane

Headquarters: Cambridge, UK

Riverlane develops quantum error correction (QEC) technology to enable fault-tolerant quantum computing. The Cambridge-based company builds hardware and software solutions and partners with quantum hardware providers and government agencies to accelerate R&D and deploy low-latency, high-throughput control systems for quantum experiments.