Hardware Engineer (Master's/PhD)

Job Title

Hardware Engineer (Master's/PhD)

Role Summary

Join the NPU hardware development team to design and verify next-generation neural processing units. Candidates will be assigned to Architecture, SoC Design, Interface Design, or RTL Verification based on background.

Work covers architecture definition, RTL/SoC design, high-speed interface integration, and comprehensive verification to deliver production silicon.

Experience Level

Entry to experienced (open to new graduates with Master's/PhD and applicants with prior design or verification experience). No specific years of experience are required.

Responsibilities

Primary responsibilities vary by assignment; representative tasks are listed below.

• Define NPU core architecture and analyze LLM computation patterns; develop performance models and cycle-level simulators for area/performance/accuracy trade-offs.
• Design SoC components including PEs, CPU integration, memory controllers, NoC/AXI interconnects; plan power/clock domains and SRAM strategies.
• Design and integrate high-speed interfaces (Die-to-Die, PCIe/UCIe, Ethernet scale-up) and HBM4 memory controllers; perform SI/PI and reliability analysis.
• Develop RTL (Verilog/SystemVerilog/Chisel) and implement DFT/MBIST, RAS, and fault-handling architectures.
• Plan and execute verification: spec-based verification, UVM environments, assertion-based checks, formal methods, and emulation/FPGA validation to achieve coverage closure.
• Collaborate closely with compiler and software teams to define HW/SW integration and execution models.

Requirements

Must-have technical skills and practical experience. Education requirements are listed separately below.

• Experience with Verilog/SystemVerilog for RTL design or verification (including research or project experience).
• Proficiency with scripting languages such as Python, TCL, or Shell.
• Familiarity with RTL verification methodologies (UVM), assertion-based verification, or formal verification preferred.
• Preferred: FPGA implementation, tape-out experience, or prior chip-design project experience.
• Preferred: Knowledge of high-speed interfaces (PCIe/UCIe, AMBA), memory hierarchies, C++ simulator implementation or PPA modeling, Chisel or RISC-V experience.

Education Requirements

Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is required.

About the Company

Company: FuriosaAI

Headquarters: Seoul, South Korea

FuriosaAI develops high-performance, energy-efficient AI inference hardware and software. Founded in 2017 by semiconductor and AI engineers, the company builds AI-native compute platforms to reduce AI energy and operational costs and operates globally with offices in Korea, Silicon Valley, and an R&D lab in Lisbon.