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Hardware Design for Test (DFT) Intern

NVIDIA
August 22, 2026
Internship
On-site
Santa Clara, California, United States
$20 - $71 USD hourly
DFT Jobs, Level - Entry or Early Career

Job Title

Hardware Design for Test (DFT) Intern

Role Summary

12-week full-time internship on NVIDIA's hardware teams focused on Design for Test (DFT). Interns will implement and validate DFT features, support test architecture and planning, and contribute to pre- and post-silicon debug to improve chip testability and quality.

Compensation: USD 20–71 per hour (varies by location, degree, and experience).

Experience Level

Entry-level internship for current graduate students. Intended for M.S. or Ph.D. students; no specific years of professional experience required.

Responsibilities

Interns will work on project-based tasks that deliver measurable results. Typical responsibilities include:

  • Design and implement DFT features and test logic for ASICs.
  • Support test architecture, DFT planning, and scan chain integration.
  • Perform static timing analysis (STA) and assist with timing closure for test paths.
  • Debug pre-silicon and post-silicon issues related to test and bring-up.
  • Develop and validate scan chain design, ATPG flows, boundary scan, and JTAG usage.
  • Implement and validate Memory BIST, Logic BIST, and compression techniques.
  • Develop test scripts and automation using scripting/programming languages.
  • Collaborate with cross-functional hardware and validation teams to deliver project milestones.

Requirements

Minimum technical skills and knowledge expected for successful candidates.

  • Coursework or internship experience in DFT, digital design, test architecture, STA, or silicon debug.
  • Familiarity with scan chain design, ATPG, boundary scan, JTAG, Memory BIST, Logic BIST, and compression methods.
  • Experience with at-speed and delay testing concepts.
  • Programming and scripting skills: Perl, TCL, Python, C or C++ and working knowledge of Linux.
  • Exposure to EDA and test tools such as Synopsys tools, TetraMAX, and Cadence Modus.
  • Ability to work full time for the 12-week internship and communicate technical results clearly.
  • Nice-to-have: prior DFT or hardware validation internship experience and familiarity with pre-/post-silicon bring-up.

Education Requirements

Must be actively enrolled and pursuing an M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field for the full duration of the internship. Resumes must include an anticipated graduation month and year.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-08-20