Hardware Design Engineer - Graphics Silicon Implementation

Job Title

Hardware Design Engineer - Graphics Silicon Implementation

Role Summary

Engineer on the Adreno GPU implementation team responsible for RTL integration through physical design for GPU cores. Work includes front-end design integration, synthesis, timing closure, formal checks, ECOs and delivery of front-end design collateral.

Collaborate with architecture, microarchitecture, DV, SoC, DFT and implementation teams across sites to meet power, performance and area goals.

Experience Level

Mid-level. The posting indicates 0–5 years of relevant industry experience; typical expectation is mid-career engineering experience.

Responsibilities

Key responsibilities include:

• Integrate and implement Adreno GPU RTL into the ASIC design flow from RTL to physical design.
• Perform RTL linting, unit-level synthesis, CDC checks and other implementation-readiness verification.
• Package, qualify and deliver front-end design collateral and netlists.
• Develop and improve front-end integration and methodology to streamline implementation.
• Perform formal verification (RTL-netlist and netlist-netlist checks) and participate in ECO generation and verification for functional and timing fixes.
• Work with synthesis and STA tools to achieve timing closure and PPA targets.
• Collaborate with cross-functional teams (architecture, DV, SoC, DFT, physical design) across multiple sites.

Requirements

Must-have and preferred skills; degrees and equivalent-experience language are listed under Education Requirements below.

• Must-have: Digital design and RTL development experience using Verilog and/or SystemVerilog.
• Must-have: Basic knowledge of synthesis, static timing analysis, timing closure, constraints, and formal verification; exposure to Synopsys Design Compiler, Conformal LEC, Synopsys Formality and Synopsys PrimeTime.
• Must-have: Familiarity with RTL integration, partitioning, transformation and clock domain crossing checks.
• Nice-to-have: UNIX plus scripting (Perl, TCL or shell), experience with physically aware synthesis flows and ECO methods for timing/functional fixes.
• Nice-to-have: Knowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC/RDC, and more advanced physical-design and STA practices.
• Nice-to-have: Strong interpersonal, analytical skills and ability to work independently in a multi-site team.

Education Requirements

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with 4+ years of relevant experience; OR Master's degree in those fields with 3+ years of relevant experience; OR PhD in those fields with 2+ years of relevant experience. Equivalent practical experience in Software/Hardware/Systems Engineering is accepted per the posted minimum-qualification options.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.