Functional Verification Engineer - SOC/IP

Role Summary

This position involves the verification of both new and existing features for AMD’s graphics processor IP, ensuring the final design is free from bugs. The role requires collaboration with various engineering teams to achieve this goal.

Experience Level

The ideal candidate should have experience in modern complex processor architecture, digital design, verification, and be comfortable working in collaborative environments with engineers across different locations.

Responsibilities

The key responsibilities include:

• Collaborate with hardware architects and firmware engineers to verify new features.
• Develop UVM-based verification environments and automated processes.
• Utilize AI tools to enhance SV/UVM test coverage.
• Implement formal verification techniques for SoC-level verification.
• Conduct power-aware verification for SoC UPF.
• Verify industry-standard cryptographic and security algorithms.
• Oversee functional verification of SoC interconnect and NoC architectures.
• Validate SoC performance concerning data path bandwidth and latencies.
• Build both directed and random verification tests meeting code coverage metrics.
• Debug test failures to identify root causes and collaborate on resolutions.

Requirements

The successful candidate will possess:

• Proficiency with UVM testbenches in Linux and Windows environments.
• Expertise in Verilog, System Verilog, and C coding.
• Knowledge of cryptographic and security algorithms.
• Familiarity with SoC-level interconnect and NoC design, and performance verification.
• Experience with high-speed bus protocols like PCIe and USB.
• Strong communication and presentation skills.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required.