Full Chip Timing/Constraints Lead

Company Overview: Advanced Micro Devices (AMD) is a global leader in high-performance computing and visualization technologies, developing innovative products for AI, data centers, PCs, and more.

Role Overview

The Full Chip Timing/Constraints Lead will be the key player in driving the Backend Full Chip Timing initiatives within the Strategic Silicon Solutions Group. This role requires collaboration with various teams to ensure designs meet timing closures and specifications effectively.

Experience Level

The ideal candidate should have over 10 years of professional experience in Physical Design and related fields, demonstrating expertise in timing analysis and signoff.

Responsibilities

• Lead the full chip timing team, overseeing constraints and timing signoff efforts.
• Manage end-to-end design delivery, ensuring timing constraints are met for SOC designs and subsystems.
• Collaborate with the SOC Architecture team to ensure clock designs meet statistical timing goals.
• Ensure proper setup of design clock requirements in Standard Delay Format (SDC).
• Assess timing margins and design variations, working with methodology teams on current and upcoming projects.
• Oversee the timing ECO phase, ensuring project milestones are achieved prior to tape out.
• Work collaboratively with CAD and EDA vendors to refine timing methodologies.

Requirements

• 10+ years of experience in STA, timing signoff, and physical design.
• Expert knowledge of industry-standard PD tools, particularly Synopsys PT/GCA.
• Familiarity with DFT timing concepts, clock implementation, and Place and Route processes.
• Proficiency in scripting with Perl/TCL/Shell/Python, and understanding of Verilog RTL design.
• Strong communication and presentation skills essential for collaborative work.

Education Requirements

Bachelor's or Master's degree in Computer, Electronics, or Electrical Engineering.