Full-Chip Senior Principal Physical Design Engineer

Job Title

Full-Chip Senior Principal Physical Design Engineer

Role Summary

Lead the full-chip physical design and methodology for next-generation, high-performance processor/SoC products targeting server, 5G/6G and networking applications. Act as full-chip lead across the implementation flow and coordinate technical deliverables with global teams and stakeholders.

Role includes ownership of physical implementation strategy, sign-off readiness, mentoring engineers, and driving automation to improve quality and productivity. This position may require eligibility to access export-controlled technology.

Experience Level

Senior — the posting specifies approximately 18–25 years of related professional experience in physical design at partition/subsystem/chip level.

Responsibilities

Accountabilities for the full-chip physical design lead role.

• Lead and coordinate full-chip RTL-to-GDSII implementation across synthesis, DFT, timing, floorplanning, CTS, placement, routing, and sign-offs.
• Plan and manage multi-million-gate hierarchical designs: sizing, partitioning, chip-top clock tree strategy, IO and bump planning.
• Ensure successful EM/IR, crosstalk, timing, PV and DFM checks and drive closure to tape-out.
• Engage with customers and global stakeholders to drive technical deliverables and manage cross-team dependencies.
• Provide technical guidance, design reviews, and mentorship for junior and mid-level engineers.
• Develop and deploy scripts, automation frameworks, and tools to improve design quality and flow efficiency.

Requirements

Key technical skills and domain experience required or strongly preferred.

• Hands-on expertise across the complete physical implementation flow and proven track record leading full-chip SoC programs from start to tape-out.
• Proficiency with RTL-to-GDS flows and methodologies; significant experience in advanced nodes (7nm, 5nm, or below).
• Extensive experience with industry tools for synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification.
• Strong scripting and automation skills (Perl, Tcl, AWK, Shell; Python experience beneficial).
• Ability to step in and resolve critical design challenges; demonstrated technical leadership and history of implementing impactful process improvements.
• Startup experience and ownership across multiple domains is valued.
• Familiarity with Verilog/VHDL is advantageous; excellent verbal and written communication skills required.

Education Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI or a closely related field (the posting specifies a Bachelor's OR Master's degree in Electronics/Electrical/VLSI). The posting pairs these degrees with the stated 18–25 years of professional physical-design experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.