Full-Chip Principal Physical Design Engineer

Job Title

Full-Chip Principal Physical Design Engineer

Role Summary

Lead full-chip physical design for high-performance processor/ASIC projects across advanced CMOS nodes. Drive technical deliverables, coordinate dependencies across RTL-to-GDS flows, and ensure successful physical sign-offs while collaborating with global engineering teams and customers.

Experience Level

Senior — 10–18 years of related professional experience in physical design at partition/subsystem/chip level.

Responsibilities

Accountable for end-to-end full-chip physical design activities and cross-team coordination.

• Serve as Full-Chip Lead: engage customers and stakeholders, plan and drive technical milestones.
• Manage multi-million-gate hierarchical designs: sizing, partitioning, chip-top clock-tree planning, IO and bump planning.
• Coordinate RTL Synthesis, DFT, Timing, Front-End, Power, and physical implementation flows to meet tape-out goals.
• Ensure sign-offs for EM/IR, crosstalk, timing, parasitics, physical verification, and DFM checks.
• Work on advanced process nodes (5nm, 3nm, 2nm) and collaborate with global teams to resolve complex issues.
• Provide technical guidance, review designs, and mentor junior engineers.
• Automate and optimize workflows using scripting and tool flows; document design decisions and results.

Requirements

Must-have technical skills and proven experience for successful execution of full-chip projects.

• Proven track record of successful tape-outs and extensive physical design experience at partition/subsystem/chip level.
• Proficiency in RTL-to-GDS flows and methodologies; significant experience with advanced nodes (7nm, 5nm, or below).
• Practical experience with industry tools for synthesis, floorplanning, placement, clock-tree synthesis, routing, and physical verification.
• Proficiency in scripting languages (Perl, TCL, AWK, Python) to automate and optimize flows.
• Familiarity with Verilog/VHDL is advantageous.
• Strong interpersonal, verbal, and written communication skills; ability to work in a collaborative global team.
• Role may require eligibility to access export-controlled technology per applicable U.S. export laws.

Education Requirements

Bachelor's or Master’s degree in Electronics, Electrical Engineering, VLSI or a closely related field. The posting specifies 10–18 years of related professional experience. No specific certifications were listed.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.