Full-Chip Physical Design Verification Engineer
TenstorrentJob Title
Full-Chip Physical Design Verification Engineer
Role Summary
Lead full-chip physical verification and signoff for advanced-node SoCs to ensure manufacturable, high-quality silicon and successful tapeouts. Work across RTL, physical design, CAD, packaging, and foundry interfaces to close DRC/LVS/DFM flows and resolve physical verification issues.
Fast-paced engineering role focused on debugging verification failures, improving PV flows, and enabling tapeout readiness.
Experience Level
Senior — typically 7–14 years of hands-on CPU/IP/SoC physical verification and tapeout closure experience.
Responsibilities
Drive physical verification signoff and closure for full-chip designs and collaborate with cross-functional teams to achieve manufacturable tapeouts.
- Lead DRC, LVS, ERC, PERC, antenna, and DFM verification for full-chip signoff.
- Debug physical verification failures and identify fixes across layout, RTL, and PD flows.
- Operate and optimize industry PV flows and tools to achieve closure and reduce iterations.
- Coordinate with RTL, PD, CAD, packaging, and foundry contacts to resolve issues and validate fixes.
- Perform reliability analyses (IR drop, EM) and advise on manufacturability and reliability mitigations.
- Develop automation and verification scripts to improve throughput and repeatability.
- Mentor engineers and help establish scalable PV methodologies and best practices.
Requirements
Key technical must-haves and valuable additions for the role.
- Must-have: 7–14 years of hands-on CPU/IP/SoC physical verification and tapeout experience.
- Must-have: Proven expertise in DRC, LVS, ERC, PERC, antenna, and DFM verification using industry-standard tools (examples: Calibre, ICV, Pegasus, Fortune/FC, Innovus).
- Must-have: Experience with advanced-node design considerations (FinFET challenges at 7nm/5nm/3nm), reliability analysis (IR drop, EM), and ESD/padring/bump/RDL integration strategies.
- Must-have: Scripting proficiency (Python, TCL) for automation and flow optimization.
- Must-have: Strong debugging skills and ability to drive closure across multiple teams and external foundry contacts.
- Must-have: Eligibility to access U.S. export-controlled technologies; employment may be contingent on citizenship/permanent residency or obtaining an export license.
- Nice-to-have: Prior leadership or mentoring experience in PV methodology, CAD tool integration, or full-chip signoff automation.
Education Requirements
BS or MS in Electrical/Electronics Engineering or related technical field (Computer Engineering, Physics, or similar). The role expects senior-level practical experience (7–14 years) in CPU/IP/SoC physical verification; degree plus relevant experience is typical.
About the Company
Company: Tenstorrent
Headquarters: Austin, Texas, United States
Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.
