Front End Design Engineer, Sr Lead

Job Title

Front End Design Engineer, Sr Lead

Role Summary

Member of the Custom/Semi-Custom Implementation (CSI) team responsible for RTL-to-GDSII implementation of CSI IPs using custom flows and methodologies. Work spans schematic-level design, front-end verification and modeling, transistor-level implementation, timing signoff, and collaboration with cross-functional teams to deliver high-speed, low-power IP blocks for SoCs.

Primary focus includes memory subsystem and datapath macro development, verification, and physical integration.

Experience Level

Senior — typically 4+ years of relevant industry experience (qualifications indicate comparable experience expectations depending on degree level).

Responsibilities

Primary responsibilities include implementation, verification, and signoff of custom IP blocks and collaboration with design and process teams.

• Schematic and transistor-level design for block-level components (e.g., register arrays, memory subsystems).
• Front-end verification and model generation; functional verification using spice/gatesim.
• Block-level formal/logic equivalence checks (LEC) and CLP/PAGLS verifications.
• Static timing analysis and timing signoff using PrimeTime.
• Physical design integration using RTL-to-GDSII flows.
• Implement power/clock gating and DFT techniques; design clock distribution and block floorplanning.
• Collaborate with Architecture, Test/Verification, CAD, Layout, Physical Design, and Process Technology teams to define and meet specs and DRC/DFM requirements.

Requirements

Must-have technical skills and experience:

• Practical transistor circuit design and block-level logic design experience for memory subsystems and datapaths.
• Experience with static timing analysis (setup, hold, MPW, transition) and timing closure.
• Design verification experience with LEC/ESPCV and simulation using Finesim and HSPICE.
• Front-end RTL design (Verilog/SystemVerilog) and familiarity with synthesis and related flows (Synopsys Design Compiler, Cadence RTL Compiler, PLDRC, PTPX).
• Physical design experience in industry-standard RTL-to-GDSII flows and tools (e.g., Synopsys ICC2, Cadence Encounter).
• IP development experience, including custom macro transistor-level design, physical integration, collateral generation, flow development, and PPA quantification.
• Scripting for automation (Perl, Python, Shell, Tcl) is a plus.

Education Requirements

Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, or a related engineering field. Qualcomm specifies degree-plus-experience minimums: Bachelor's +3 years hardware engineering experience, Master's +2 years, or PhD +1 year (equivalent practical experience may be acceptable where indicated).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.