Front End CAD Principal Engineer

Job Title

Front End CAD Principal Engineer

Role Summary

Lead CAD engineer in Central Engineering responsible for developing next-generation automated design flows and associated tools that support multiple business units. The role focuses on flow architecture, integration with infrastructure teams, and delivering scalable, modular CAD platforms.

The position requires collaboration with flow and infrastructure teams, driving CAD architectural decisions across stakeholders, and providing technical leadership for complex RTL-to-gate verification and integration tasks.

Experience Level

Senior — typically 10–15 years with a Bachelor's, or 5–10 years with a Master's/PhD (as specified in Education Requirements).

Responsibilities

Primary responsibilities include designing, deploying, and supporting automated CAD flows and ensuring their integration and scalability.

• Develop and maintain automated CAD flows tailored to multiple business units' needs.
• Deploy and support modular, highly automated flow components and add-on tools.
• Collaborate with infrastructure and flow teams to integrate tools into the broader CAD platform.
• Provide technical leadership on CAD architecture and align stakeholders across business units on key decisions.
• Design innovative solutions for complex design challenges and improve flow robustness and performance.
• Support RTL qualification, integration, release processes, and ECO implementation where applicable.

Requirements

Must-have technical skills, tools, and behaviors for success in this role. Degree and years of experience are listed separately in Education Requirements.

• Strong scripting skills in Tcl and Python for flow development.
• Proficiency in Verilog / SystemVerilog for design and verification.
• Experience with RTL linting tools and clock domain crossing (CDC) analysis.
• Experience using git for revision control.
• Good analysis and problem-solving skills; able to propose out-of-the-box solutions.
• Effective verbal and written communication; able to work across teams and drive alignment.
• Team player with a strong willingness to learn new skills and technologies.

Nice-to-have / Preferred:

• Knowledge of equivalence checking (RTL-to-gates and gates-to-gates) and tools such as LEC or Formality.
• Experience with UPF definitions and multi-power-domain implementations.
• Familiarity with writing, validating, and debugging timing constraints (SDC) and synthesis-to-P&R integration.
• Experience implementing Functional ECOs and setting up ECO flows (LEC ECO or Formality ECO).

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or related field with 10–15 years of related professional experience; OR Master’s degree or PhD in Computer Science, Electrical Engineering, or related field with 5–10 years of related professional experience. No certifications were specified. The posting does not state an explicit allowance for equivalent practical experience in lieu of a degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.