Front End ASIC RTL/Logic Verification Engineer

Job Title

Front End ASIC RTL/Logic Verification Engineer

Role Summary

Design and execute RTL/logic verification plans for front-end ASIC blocks to ensure functional correctness and quality before IP-SoC integration. Work with customers and SoC teams to support integration, debug failing RTL tests, and implement corrective measures.

Experience Level

Mid-level. No years-of-experience guidance specified.

Responsibilities

Primary responsibilities include verifying RTL designs, debugging, and supporting integration with SoC customers.

• Develop and execute verification plans to validate design features.
• Analyze failing RTL tests, implement fixes, and verify corrective measures.
• Support SoC customers and integration teams to ensure correct IP-SoC handoff.
• Drive quality assurance practices for reliable IP delivery.
• Collaborate with design and validation teams during simulation and debug cycles.

Requirements

Must-have technical skills and interpersonal capabilities.

• Proficiency in RTL coding using HDL languages (e.g., VHDL, Verilog/SystemVerilog).
• Familiarity with logic simulation and debug environments and workflows.
• Strong communication, problem-solving, investigation, and analytical skills.
• Experience working with IP integration or supporting SoC-level integration activities.
• Nice-to-have: scripting skills to automate verification tasks.

Education Requirements

BS, MS, or PhD in Electronics Engineering.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.