FPGA Engineer — RTL / VHDL / Verilog & Timing Expert

Job Title

FPGA Engineer — RTL / VHDL / Verilog & Timing Expert

Role Summary

Design and develop FPGA logic using VHDL and/or Verilog for engineering consulting projects. Work with synthesis and implementation tools (Vivado or Quartus) to deliver RTL designs that meet functional and timing requirements.

Position is based in Napoli (Campania) and embedded in a technical engineering consulting team. Work will include RTL implementation, timing closure, and collaboration with cross-functional teams.

Experience Level

Mid-level. The posting does not specify years of experience.

Responsibilities

Key responsibilities include:

• Develop RTL designs in VHDL and/or Verilog for FPGA targets.
• Perform synthesis, place-and-route, and timing closure using Vivado or Quartus.
• Conduct static timing analysis and optimize designs to meet timing constraints.
• Integrate and verify FPGA blocks with system-level requirements and interfaces.
• Document designs, implementation decisions, and test results; collaborate with engineering teams.

Requirements

Must-have technical skills and experience:

• Proven experience in FPGA design and RTL development using VHDL and/or Verilog.
• Hands-on experience with Vivado or Quartus toolchains for synthesis and implementation.
• Experience with static timing analysis and timing closure techniques.
• Practical ability to integrate FPGA logic with system interfaces and perform basic verification.
• Good technical communication and teamwork skills in an engineering environment.

Nice-to-have:

• Previous consulting or project-based engineering experience.
• Familiarity with testbench-based verification or lab bring-up.
• Italian language proficiency.

Education Requirements

Bachelor's degree in Electronic Engineering (laurea in ingegneria elettronica) is required.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.