FPGA Engineer — RTL/VHDL/Verilog & Timing Expert

Job Title

FPGA Engineer — RTL/VHDL/Verilog & Timing Expert

Role Summary

Engineer responsible for designing and implementing FPGA logic using RTL languages (VHDL and/or Verilog). The role sits within an engineering consultancy team supporting FPGA development projects and focuses on correctness, performance and timing closure.

Experience Level

Mid-level. Specific years of experience not stated.

Responsibilities

Primary duties include implementation, verification and delivery of FPGA designs.

• Design and develop FPGA RTL using VHDL and/or Verilog.
• Implement synthesis flows and target device constraints with tools such as Vivado or Quartus.
• Perform timing analysis and work toward timing closure.
• Create and execute simulation and verification testbenches for functional validation.
• Support integration and bring-up activities, including lab testing and debugging.
• Prepare technical documentation and design reviews.

Requirements

Core technical skills required; additional desirable skills listed where applicable.

• Must-have: Practical experience coding RTL in VHDL and/or Verilog for FPGA designs.
• Must-have: Hands-on experience with FPGA toolchains such as Xilinx Vivado or Intel Quartus.
• Must-have: Experience with timing analysis and timing-closure techniques.
• Nice-to-have: Experience with simulation/verification tools and testbench development.
• Nice-to-have: Experience with board bring-up, lab debugging, or embedded interfaces.

Education Requirements

Bachelor's degree in Electronic Engineering (laurea in ingegneria elettronica) required.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.