FPGA Engineer (Mid-Level)

Job Title

FPGA Engineer (Mid-Level)

Role Summary

Design, implement, and verify FPGA logic on AMD Xilinx devices for the Palm Bay engineering team. Deliver features end-to-end and integrate firmware with systems, software, and test teams.

Position supports defense projects and requires an active security clearance.

Experience Level

Mid-level. The posting expects prior FPGA engineering experience and demonstrated RTL skills (VHDL/Verilog); no explicit years-of-experience were provided.

Responsibilities

Key responsibilities include:

• Design and implement RTL for AMD Xilinx FPGAs using VHDL and/or Verilog.
• Develop and execute simulations, testbenches, and verification plans.
• Perform synthesis, timing analysis, and timing-closure activities.
• Debug hardware and firmware in the lab; perform bring-up and fault diagnosis in a Linux environment.
• Integrate FPGA logic with system-level software and test frameworks.
• Maintain documentation, constraints, and design reviews for delivered features.
• Work on defense-related projects under required security controls.

Requirements

Must-have and preferred qualifications:

• Must-have: Strong RTL skills in VHDL and/or Verilog.
• Must-have: Experience with timing closure, synthesis, and static timing analysis on Xilinx devices.
• Must-have: Hands-on lab debugging and board bring-up experience in a Linux environment.
• Must-have: Ability to own features end-to-end and collaborate with systems, software, and test teams.
• Must-have: Active security clearance required.
• Nice-to-have: Experience with Vivado/ISE toolflow, scripting for build/verification, and hardware bring-up tools.

Education Requirements

Not specified.

About the Company

Company: Harris Geospatial Solutions

Headquarters: Melbourne, FL, United States

Provider of geospatial intelligence and location-based solutions, developing software and hardware for mapping, imagery, and geospatial analysis used in defense, public safety, and commercial markets.