FPGA Engineer - Intern (Asia)

Job Title

FPGA Engineer - Intern (Asia)

Role Summary

Work on FPGA design and implementation for ultra-low-latency trading systems within small engineering teams at Citadel Securities. The role focuses on developing, validating, and deploying FPGA solutions that improve trading system performance and execution speed.

Experience Level

Internship — entry-level; 12-week program for students pursuing undergraduate or graduate studies.

Responsibilities

Primary responsibilities include:

• Design, implement, and test FPGA logic and subsystems (RTL) for production trading systems.
• Participate in architecture, simulation, synthesis, and system integration activities.
• Run hardware validation, static analysis and performance tuning to reduce latency and improve throughput.
• Collaborate with traders, researchers, and senior engineers to translate requirements into FPGA solutions.
• Document designs and test results; communicate findings to team members.

Requirements

Technical skills and experience expected for interns:

• Experience with SystemVerilog or VHDL.
• Familiarity with FPGA synthesis flows, simulation, and RTL coding.
• Background in hardware validation, testing, and systems integration.
• Knowledge of hardware architecture and static analysis techniques.
• Proficiency in scripting or programming (Python, C, Tcl, Bash) is a plus.
• Strong written and verbal communication skills and problem-solving aptitude.

Education Requirements

Pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Citadel Securities

Headquarters: Chicago, Illinois, United States

Citadel Securities is a global market maker and trading firm providing electronic market making, execution services, and trading technology across equities, options, and fixed income. The firm builds low-latency systems and liquidity solutions for institutional clients.