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FPGA Development Tools Engineer

Altera
May 05, 2026
Full-time
On-site
Penang, Penang, Malaysia
RTL Design Jobs, Level - Senior

Job Title

FPGA Development Tools Engineer

Role Summary

Lead development, modeling, and validation of FPGA IP and simulation models within the Quartus Prime toolchain. This is a hands-on leadership role responsible for technical direction, design reviews, debugging, and improving IP quality, simulation accuracy, and engineering productivity.

Collaborate with verification, fitter/compilation, and timing teams to ensure consistency between simulation models and hardware, and to integrate models into compilation and regression flows.

Experience Level

Senior — typically 8–12+ years of relevant experience in FPGA design, IP development, or verification.

Responsibilities

Primary responsibilities include technical leadership, IP development, verification strategy, debugging, and Quartus flow integration.

  • Set technical direction and lead design and architecture reviews for IP and simulation models.
  • Design and implement FPGA IP in RTL (Verilog/SystemVerilog/VHDL) and develop behavioral and cycle-accurate simulation models.
  • Define and enforce verification methodologies (SystemVerilog, assertion-based verification); contribute to testbench architecture, coverage, and regression systems.
  • Debug complex issues across simulation, fitter, and timing analysis; identify root causes and drive fixes.
  • Integrate simulation models with compilation, fitter, and timing closure flows; improve tool usability and debuggability.
  • Champion automation and productivity improvements (Python, Tcl, regression infrastructure, AI-assisted workflows where applicable).
  • Mentor engineers and raise team capability in debugging, design quality, verification practices, and system-level thinking.

Requirements

Core requirements and desirable skills. Degree requirements are listed separately under Education Requirements.

  • Must-have: 8–12+ years experience in FPGA design, IP development, or verification.
  • Must-have: Strong hands-on expertise in RTL design using Verilog/SystemVerilog/VHDL.
  • Must-have: Experience with simulation and verification methodologies and tools.
  • Must-have: Deep experience with Altera Quartus Prime or equivalent FPGA toolchains.
  • Must-have: Proven ability to debug complex system-level issues and lead technical initiatives.
  • Nice-to-have: Experience with automation (Python, Tcl), regression frameworks, and AI-assisted workflows.
  • Nice-to-have: Experience in testbench architecture, coverage-driven verification, assertion-based verification, and cycle-accurate modeling.
  • Nice-to-have: Strong understanding of fitter outputs and timing analysis.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.


About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.

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Date Posted: 2026-05-04