FPGA Development Tools Engineer — College Graduate

Job Title

FPGA Development Tools Engineer — College Graduate

Role Summary

Entry-level engineering role to develop, execute, and automate device and timing model validation tests within Quartus Prime flows. The position focuses on validating FPGA device models, timing models, and related collateral used by synthesis, place-and-route, and timing analysis.

You will work with modeling, device, and software teams to maintain model quality, correctness, and regression stability across FPGA device families by combining EDA flow execution, test automation, and software development.

Experience Level

Entry-level — recent college graduate. Suitable for candidates within 1 year of graduation (0–1 years professional experience).

Responsibilities

Deliver and automate tests and infrastructure to validate device and timing models across compilation, fitting, and timing flows.

• Develop test plans and execute targeted and regression tests for multiple FPGA device families, configurations, and corner conditions.
• Run end-to-end Quartus projects to exercise synthesis, fitter, and timing signoff; maintain golden reference results and triage QoR/timing/resource deltas.
• Package and maintain reproducible test kits and reference designs for regression runs.
• Create and maintain automation and modeling tools (C++, Tcl, Python, bash) for test generation, execution, log mining, and reporting.
• Develop and maintain C++ device model libraries representing FPGA architecture blocks used by synthesis and timing flows.
• Integrate tests and validation into CI pipelines with pass/fail gates and artifact tracking.
• Analyze failures across RTL, constraints, tool behavior, and model implementations; isolate root causes and validate fixes.
• Track quality metrics (pass rate, coverage, defect density) and document test plans, runbooks, and acceptance criteria.

Requirements

Must-have technical skills and experience required for daily tasks; preferred items are listed separately.

• Must-have: Foundation in digital design principles (combinational/sequential logic, clocking, resets, pipelining).
• Must-have: Exposure to FPGA/ASIC flows: RTL (Verilog/SystemVerilog or VHDL), synthesis, static timing analysis, and constraints (SDC).
• Must-have: Proficiency in at least one scripting language (Tcl or Python) and working knowledge of C++ for debugging or implementing device models.
• Must-have: Familiarity with Linux development environments and build workflows.
• Must-have: Strong problem-solving skills and ability to interpret tool logs and timing reports; effective written communication for documentation and defect reporting.
• Nice-to-have: Experience developing or maintaining C++ libraries for hardware or device modeling (DSP, memory, timing models).
• Nice-to-have: Experience with Quartus Prime (TimeQuest, fitter concepts), version control (Git), and CI systems (Jenkins/GitLab CI).
• Nice-to-have: Familiarity with device concepts (speed grades, PVT corners, IO standards, clocking networks) and timing signoff concepts.
• Nice-to-have: Coursework or projects involving FPGA boards, EDA tools, or regression test environments.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field; position targeted at candidates within one year of graduation. (No certifications specified.)

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.