FPGA Development Tools Engineer - College Graduate

Job Title

FPGA Development Tools Engineer - College Graduate

Role Summary

Entry-level engineering role responsible for validating and automating FPGA device and timing model tests within Quartus Prime flows. Works with synthesis, place-and-route, and timing analysis toolchains to ensure model correctness and regression stability across device families.

Role blends digital design fundamentals, EDA flow execution, software development, and test automation to maintain model quality and test infrastructure.

Experience Level

Entry-level (College graduate). Suitable for candidates within one year of graduation.

Responsibilities

Primary responsibilities focus on planning, executing, and automating tests and maintaining test infrastructure for device and timing model validation.

• Create and execute test plans for device and timing model validation across Quartus Prime components (Compilation, Fitter, TimeQuest, Assembler).
• Run targeted and regression tests across FPGA device families, configurations, and corner conditions; validate SDC interpretation, timing arcs, and model parameterization.
• Build and run end-to-end Quartus projects; maintain golden reference results and triage QoR, timing, resource, and warning/error deltas.
• Package and maintain reproducible test kits and reference designs for regression runs.
• Develop and maintain automation and modeling tools using C++, Tcl, Python, and bash for test generation, execution, log mining, and reporting.
• Integrate tests into CI pipelines (e.g., Jenkins/GitLab CI) with pass/fail gates and artifact tracking; develop utilities for parameterization and coverage expansion.
• Analyze failures across synthesis, fitter, timing, and models; isolate root causes and collaborate with modeling, device, and software teams to validate fixes.
• Track quality metrics (pass rate, coverage, defect density) and produce documentation: test plans, runbooks, and user guides.

Requirements

Must-have technical skills and practical experience for successful performance in this role. Preferred items are listed separately.

• Understanding of digital design fundamentals: combinational and sequential logic, clocking, resets, and pipelining.
• Exposure to FPGA/ASIC flows and tools: RTL (Verilog/SystemVerilog or VHDL), synthesis, static timing analysis, and constraints (SDC).
• Proficiency in at least one scripting language (Tcl or Python) and working knowledge of C++ for developing or debugging models and tools.
• Familiarity with Linux development environments and build workflows.
• Ability to interpret tool logs and timing reports; strong debugging and problem-solving skills.
• Effective written communication for documentation and clear defect reporting.

Nice-to-have:

• Experience developing or maintaining C++ libraries for hardware or device modeling (DSP, memory, timing models).
• Experience with Altera Quartus Prime (TimeQuest, fitter concepts) and hands-on FPGA tool experience.
• Experience with version control (Git) and CI systems (Jenkins/GitLab CI).
• Familiarity with device concepts such as speed grades, PVT corners, IO standards, and clocking networks; basic timing signoff knowledge.
• Coursework or projects involving FPGA boards, EDA tools, or regression test environments.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field (within one year of graduation). No certifications specified.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.