Job Title
FPGA Development Intern β Fall 2026 (SystemVerilog & UVM)
Role Summary
Contribute to FPGA design and verification for optical networking products on a hardware engineering team. The role focuses on SystemVerilog RTL development, UVM-based verification, implementation support, and lab bring-up under mentorship.
Experience Level
Entry-level internship; no prior full-time professional experience required.
Responsibilities
Primary responsibilities include:
- Develop and modify RTL in SystemVerilog for FPGA implementation.
- Author and maintain UVM testbenches and directed/random verification tests.
- Run simulations, debug failures, and analyze waveforms and logs.
- Support synthesis and implementation flows and constraint development.
- Participate in hardware bring-up, lab debugging, and integration testing.
- Document design and verification work and participate in design/review meetings.
Requirements
Core technical skills and behaviors expected:
- Practical experience with SystemVerilog and UVM for verification (must-have).
- Familiarity with FPGA toolflows (synthesis/place-and-route) and version control systems.
- Basic scripting ability (Python, TCL, or similar) for test automation and tool integration.
- Strong written and verbal communication; ability to collaborate across teams.
- Self-motivated, detail-oriented, and receptive to mentorship and feedback.
- Nice-to-have: experience with Vivado/Quartus, ModelSim/Questa, or domain knowledge of optical networking.
Education Requirements
Pursuing a Bachelors degree in Electrical Engineering or Computer Engineering. The posting specifies foundational knowledge of circuit design. This is a Fall 2026 internship opportunity.
About the Company
Company: Ciena
Headquarters: Hanover, MD, United States
Global networking systems, services and software company that designs and supplies optical and packet networking, network automation, and software-defined networking solutions for telecommunications service providers and enterprises.

Date Posted: 2026-05-20