FPGA Design & Formal Verification Engineer

Role Summary

The Advance Formal Verification team at AMD specializes in formal verification methodologies for various IPs including PCIe and high-speed inter-chiplet connections. We are seeking FPGA Design & Formal Verification Engineers who are adept in IP verification and possess experience with advanced verification technologies.

Experience Level

This position is suitable for both junior and senior engineers, with responsibilities scaling based on experience. Senior roles will involve team leadership and mentorship.

Responsibilities

• Collaborating with design teams to clarify design intents.
• Creating and executing formal verification plans.
• Writing and debugging properties to verify designs and analyzing signatures.
• Optimizing verification runtime through effective formal techniques.
• Reporting on status and improvement progress during reviews.
• Leading and coordinating team verification activities as a senior engineer.
• Mentoring junior staff and enhancing verification setups based on performance feedback.

Requirements

Candidates must have a strong background in digital systems design and formal verification methodologies. Experience in high-speed protocols and FPGA debugging is preferred.

Education Requirements

A BS or higher degree in Electronics, Electrical, or Computer Engineering is desired.