FPGA Design and Verification Engineer

Role Overview

The position involves being part of the Advance Formal Verification team at AMD, focused on formal verification methodologies for various IPs. You will engage in the latest verification technologies to ensure high-quality design standards.

Experience Level

This position is aimed at individuals with significant experience in formal verification, specifically those capable of leading small teams for senior roles.

Key Responsibilities

• Collaborate with architects and designers to ascertain design intents.
• Create and execute formal verification plans for design blocks.
• Write and debug properties for design verification, analyze signatures, and work towards resolutions.
• Optimize runtime via formal techniques.
• Report on status and progress regularly.
• Enhance formal setups based on feedback and metrics.
• For senior roles: Lead verification activities, mentor junior engineers, and manage complex formal challenges.

Required Qualifications

Ideal candidates will possess:

• Proficiency in designing FPGA-based digital systems.
• Experience in Verilog/SystemVerilog/VHDL for FPGA designs.
• Strong background in formal property verification and related methodologies.
• Familiarity with high-speed protocols like PCIe and USB.

Education Requirements

A BS or higher degree in Electronics/Electrical or Computer Engineering is preferred.