FPGA/ASIC Verification Engineer

Job Title

FPGA/ASIC Verification Engineer

Role Summary

Verify FPGA-based designs and embedded firmware for tactical radio communication systems used by military and first responders. Work on a cross-functional engineering team to plan and execute coverage-driven verification from test planning through closure.

Position offers flexible schedules (9/80 or standard 5/8) and focuses on hands-on verification using SystemVerilog and UVM.

Experience Level

Mid-level — the role expects multiple years of FPGA/ASIC verification experience. See Education Requirements for explicit years-of-experience guidance.

Responsibilities

Primary responsibilities include developing verification plans, testbenches, and tests to verify FPGA designs meet system requirements.

• Analyze requirements and create high-level and detailed verification test plans.
• Develop self-checking SystemVerilog test benches within a UVM framework.
• Implement Agents, test sequences, covergroups, predictors, and scoreboards.
• Write randomized and directed tests to drive functional coverage closure and iterate with design teams.
• Verify FPGA/ASIC designs for embedded radio product development projects in collaboration with hardware, firmware, and systems teams.
• Prepare and present technical briefings, design and implementation reviews, and status to internal and external stakeholders.
• Support verification planning, execution, and documentation through closure.

Requirements

Key technical must-haves and useful additional skills. See Education Requirements for degree and years guidance.

• Must-have: Hands-on FPGA/ASIC verification experience; proficiency in SystemVerilog and UVM; experience with coverage-driven verification methodologies; ability to develop self-checking testbenches, randomized and directed tests, and achieve functional coverage goals.
• Must-have: Experience working with cross-functional teams and producing verification artifacts and technical briefings; ability to obtain and maintain U.S. security clearance.
• Nice-to-have: Mentor Graphics verification tool experience, FPGA/ASIC RTL design background, Ethernet packet-processing design experience, familiarity with cryptographic algorithms for embedded communications.
• Nice-to-have: Proficiency in object-oriented programming (C++, Java), scripting (Bash, Perl, Python, Tcl), Linux environments, and knowledge of industry interfaces (Ethernet, AXI, SPI).
• Communication: Strong technical writing and ability to communicate complex technical concepts clearly.

Education Requirements

Bachelor's degree with a minimum of 6 years of related experience; or a graduate degree with a minimum of 4 years of related experience; in lieu of a degree, a minimum of 10 years of related experience is acceptable. No specific fields of study or certifications were specified in the posting.

About the Company

Company: Grammar

Engineering firm focused on FPGA/ASIC verification and embedded firmware for secure tactical radio communication systems used by military and first responders.