Formal Verification Engineer

Job Title

Formal Verification Engineer

Role Summary

The Formal Verification Engineer will lead formal verification efforts for Infinity Fabric network components, verifying configurable switches and die-to-die interconnect across AMD products. The role focuses on proving correctness, finding corner-case bugs, and improving design quality.

The role collaborates closely with RTL designers, simulation verification engineers, and architects to integrate formal methods into verification plans and to mentor junior engineers.

Experience Level

Senior — minimum 8+ years of design verification experience with a strong focus on formal verification.

Responsibilities

Primary responsibilities include:

• Develop and execute formal verification strategies for property checking (FPV), connectivity checking (CC), register verification (FRV), and sequential equivalence checking (SEQ).
• Write, review, and debug SystemVerilog Assertions (assumptions, assertions, and cover properties) to verify complex design behaviors.
• Drive convergence of formal proofs using abstraction, complexity reduction, and assume-guarantee reasoning.
• Collaborate with RTL designers and architects to define verification plans that combine formal and simulation-based approaches.
• Identify and champion opportunities to apply formal methods to new design blocks and to shift verification left.
• Develop reusable formal verification infrastructure, including constraint libraries, parameterized property templates, and automated regression flows.
• Mentor and guide MTS and junior engineers in formal verification techniques and best practices.

Requirements

Must-have qualifications:

• Minimum 8+ years experience in design verification with a strong focus on formal verification.
• Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification.
• Practical experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
• Experience driving proofs to convergence using abstraction and assume-guarantee techniques.
• Proven ability to collaborate with RTL designers, simulation teams, and architects to produce formal-inclusive verification plans.
• Legal authorization to work in the United States; this role is not eligible for visa sponsorship.

Nice-to-have:

• Hands-on experience with VC Formal (Synopsys) and/or JasperGold (Cadence).
• Familiarity with scripting languages for flow automation (TCL, Python, Perl).

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.