Field-Programmable Gate Arrays Engineer

Job Title

Field-Programmable Gate Arrays Engineer

Role Summary

Implement communication waveforms on FPGA platforms and deliver production-ready baseband designs for tactical radios and secure communication products. The role sits on an embedded/FPGA engineering team working with RF transceivers and SoC platforms to move algorithms into synthesizable RTL and validated hardware.

Experience Level

Mid-level. The role expects approximately 3+ years of FPGA development experience in Verilog/VHDL for DSP or communication systems.

Responsibilities

Deliver FPGA-based baseband transmit and receive chains from algorithmic models through RTL and hardware verification.

• Design and implement single-carrier and multi-carrier (OFDM) waveforms on FPGA platforms.
• Build complete TX and RX baseband chains (bits to RF interface and back).
• Convert MATLAB/Python floating-point models into fixed-point, synthesizable RTL.
• Integrate DSP blocks with RF transceivers (e.g., AD9361/AD9364) and ARM processors on Zynq/MPSoC platforms.
• Verify designs in simulation and on hardware; achieve timing closure for production builds.

Requirements

Core technical skills and domain experience required for the role.

• 3+ years of FPGA development in Verilog/VHDL for DSP or communication systems.
• Hands-on experience implementing QPSK modulation and demodulation on FPGA.
• Proven experience designing single-carrier and multi-carrier waveforms.
• Strong understanding of fixed-point arithmetic, bit-width analysis, and resource/latency trade-offs.
• Transmit-chain capabilities: scrambling, CRC, FEC encoding (convolutional/LDPC/Turbo), interleaving, symbol mapping (BPSK/QPSK/QAM), preamble/pilot insertion, pulse shaping (RRC), interpolation, CIC/FIR filters, NCO, digital up-conversion, OFDM IFFT, cyclic-prefix insertion.
• Receive-chain capabilities: digital down-conversion, decimation, AGC, DC offset correction, packet detection/frame synchronization, timing recovery, carrier frequency/phase recovery, channel estimation and equalization, OFDM FFT and CP removal, FEC decoding (Viterbi, LDPC), de-interleaving, descrambling.
• Familiarity with toolchain: Xilinx Vivado, Vitis HLS; AXI4 / AXI-Stream interfaces; MATLAB/Simulink and Python/NumPy; ModelSim/QuestaSim; on-hardware debug tools (ILA/ChipScope).
• Eligibility: Indian citizen (required for defence programmes).

Nice-to-have:

• Frequency hopping or spread-spectrum waveform experience.
• MIMO, MANET, or tactical radio domain experience.
• RFSoC, GNU Radio, or embedded Linux exposure.

Education Requirements

B.Tech or M.Tech in Electronics & Communication Engineering, Electrical Engineering, or a related technical field; equivalent practical experience in FPGA/communications may be acceptable.

About the Company

Company: Naadyx Solutions

Headquarters: Hyderabad, India

Naadyx Solutions is an Indian deep-tech defence electronics company that develops tactical software-defined radios, counter-UAS systems and secure communication products for the Indian armed forces.