Engineer / Senior Engineer / Principal — NAND CMOS DTCO
Work on Design-Technology Co-Optimization (DTCO) for NAND CMOS process and device integration. Influence PPAC (performance, power, area, cost) targets, translate them into design rules and device/test monitors, and enable models used by design teams.
Position is based in San Jose, CA; full-time role within Micron's process and device engineering organization focused on closing PPAC gaps and model enablement.
Senior — principal-level engineering role. Specific years of experience not stated.
Primary responsibilities include:
Must-have skills and responsibilities inferred from the posting:
Nice-to-have: semiconductor manufacturing experience, interconnect RC and reliability analysis.
Not specified.
Company: Micron Technology
Headquarters: Boise, Idaho, USA
Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.
