Engineer, Physical Design
RenesasJob Title
Engineer, Physical Design
Role Summary
Join the Physical Design team in Bengaluru to support RTL-to-GDSII implementation for ASIC/SoC projects at advanced technology nodes. The role focuses on practical physical design tasks (synthesis, placement, CTS, routing, timing closure) under the guidance of senior engineers and contributes to chip tape-outs.
Experience Level
Entry-level — targeted at recent graduates (early-career). Suitable for B.Tech / M.Tech graduates seeking an initial role in physical design.
Responsibilities
Day-to-day responsibilities include implementation, verification, and automation tasks to support physical design and timing closure.
- Support RTL-to-GDSII flow: synthesis, floor planning, placement, clock tree synthesis, routing, and sign-off.
- Assist in Static Timing Analysis and timing closure across multi-mode, multi-corner scenarios.
- Work with senior engineers on timing optimization, congestion analysis, and power optimization.
- Develop and refine design constraints (SDC) for synthesis and STA.
- Perform basic physical verification checks (DRC, LVS) and assist in debugging issues.
- Collaborate with RTL, DFT, and other teams to meet design quality and timelines.
- Contribute to automation and scripting (Python/Tcl/Perl) to improve design efficiency.
- Document learnings and participate in knowledge-sharing sessions.
Requirements
Key technical skills and attributes required; degrees are summarized separately in Education Requirements.
- Must-have: Strong fundamentals in digital electronics, CMOS/VLSI design, and timing concepts (setup, hold, basic clocking).
- Must-have: Basic understanding of the ASIC design flow and synthesis/STA concepts.
- Must-have: Exposure to EDA tools (academic or internship) such as Synopsys or Cadence toolsets (e.g., Design Compiler, Innovus, ICC2, PrimeTime).
- Must-have: Programming/scripting experience in Python, Tcl, or C++ for automation tasks.
- Nice-to-have: Academic or internship experience in physical design, STA, or synthesis; coursework or projects in ASIC/FPGA/VLSI CAD.
- Nice-to-have: Knowledge of low-power design techniques (clock gating) and MMMC concepts.
- Strong analytical skills, eagerness to learn, attention to detail, and effective teamwork and communication.
Education Requirements
B.Tech or M.Tech in Electronics & Communication Engineering (ECE), Electrical Engineering (EE/EEE), or related technical fields. Candidates are expected to be recent graduates from premier institutes (IITs, NITs, IISc, BITS, or equivalent universities).
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
