Engineer II, Physical Design

Job Title

Engineer II, Physical Design

Role Summary

Execute and optimize RTL-to-GDS implementation flows for high-performance CPU cores, with primary responsibility for block-level implementation and PPA (Power, Performance, Area) closure on advanced FinFET process nodes. Work within a methodology-focused team to deliver production-ready flows and design sign-off.

Experience Level

Entry-level (Engineer II) — typically 2+ years of hands-on physical design/methodology experience.

Responsibilities

Deliver block-level physical implementation and maintain production flows; collaborate with methodology, IP, and core teams to achieve PPA targets.

• Implement, validate, and maintain RTL-to-GDS recipes using Synopsys Fusion Compiler and established methodology.
• Own end-to-end implementation of medium-sized CPU sub-blocks from RTL synthesis through GDS sign-off.
• Drive block-level PPA closure using timing-driven placement, CTS, and routing techniques.
• Apply ML-based optimization tools for design space exploration and PPA improvement.
• Identify, debug, and resolve flow and tool-related issues at the block level.
• Partner with IP teams (SRAM, standard cells) and technical leads to model PPA impacts.
• Develop and maintain Tcl/Python automation to improve flow efficiency and repeatability.

Requirements

Core technical qualifications (must-have) and relevant preferred skills.

• Must-have: 2+ years of hands-on physical design/methodology experience in digital implementation.
• Must-have: Practical experience with FinFET nodes such as N5/N3.
• Must-have: Hands-on proficiency with Synopsys implementation and signoff tools (Fusion Compiler, ICC2, PrimeTime, StarRC).
• Must-have: Strong understanding of floorplanning, pin assignment, and timing budgeting in hierarchical designs.
• Must-have: High proficiency in Tcl and Python for flow customization, debugging, and data analysis.
• Must-have: Demonstrated ability to analyze and resolve complex timing, power, and congestion issues.
• Preferred: Familiarity with N2/GAAFET challenges.
• Preferred: Experience deploying ML optimization tools (e.g., DSO.ai) for PPA optimization.
• Other: Excellent communication and teamwork; role requires background/reference checks, proof of right to work in India, and may require export-control authorization.

Education Requirements

Not specified.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.