Emulation Engineer

Job Title

Emulation Engineer

Role Summary

Define and deliver emulation infrastructure, flows, and debug methodology for connectivity SoCs. Work on emulation bring-up, HW/SW co-emulation, and reusable tooling that spans RTL, firmware, software, and vendor EDA flows.

Role sits on the Emulation team and collaborates with architecture, RTL, DV, SoC, firmware, drivers, validation, and EDA/vendor teams. Requires on-site presence in Mountain View (Tuesdays–Thursdays).

Experience Level

Senior / Staff level (senior). Years of experience not specified; targets experienced engineers with substantial emulation and system-level validation background.

Responsibilities

Primary responsibilities include building emulation flows, integrating models, and enabling system-level debug and automation:

• Define and execute emulation strategies and test plans for complex connectivity SoCs.
• Bring up and debug large-scale models on commercial emulation platforms (e.g., Cadence Palladium, Zebu, Veloce).
• Integrate adapters, memory models, VIPs, and build custom transactors for PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, QSPI, etc.
• Develop HW/SW co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and tests.
• Build reusable transactors, agents, stubs, bridges, checkers, and acceleration flows.
• Optimize emulation performance: compile-time reduction, partitioning, clocking strategy, regression scheduling, and resource utilization.
• Automate regression triage, debug, model usability, and engineering productivity workflows.
• Develop practical LLM-based tooling for log analysis, waveform triage, and debug assistance.
• Collaborate across architecture, RTL, DV, firmware, drivers, kernel, validation, and EDA/vendor teams.

Requirements

Must-have skills and experience:

• Hands-on experience with SoC emulation or system-level validation.
• Experience with at least one commercial emulation platform (e.g., Palladium).
• Working Verilog/SystemVerilog and waveform-debug skills; ability to develop custom transactors or agents.
• Strong software and automation skills: Python plus one or more of C, C++, Rust, Tcl, or shell.
• Proven ability to build tools and infrastructure, not just run flows.
• Strong system-level debug instincts spanning RTL, firmware, and software.
• Ability to work independently and across functional teams.

Nice-to-have:

• UVM or hybrid SoC testbench development.
• Integrating cycle-accurate or software/reference models into emulation/DV flows.
• Rust in verification/emulation flows.
• Bazel or large-scale build/regression systems.
• Experience with connectivity SoCs: PCIe/CXL, Ethernet, DMA, HBM, chiplets, interconnect fabrics.
• Firmware or driver bring-up on emulation platforms.
• Scaling emulation or verification infrastructure across projects.
• Experience using AI/LLMs to build engineering tools beyond prompting.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.