EDA Tooling Release and Sign-off Engineer

Job Title

EDA Tooling Release and Sign-off Engineer

Role Summary

Join the HPC Controller IP infrastructure and release team to own EDA tooling, flow automation, and the product release and sign-off process for complex soft IP. The role focuses on packaging, release testing, quality gates, and producing repeatable release collateral.

Experience Level

Entry-level - typically expects about 2+ years of relevant experience or equivalent project experience.

Responsibilities

Primary responsibilities include managing and automating release workflows, validating deliverables, and driving releases to sign-off.

• Own and execute the product release process: assemble and package deliverables and produce release collateral.
• Run release regressions and quality gates; verify package contents and sign off deliverables.
• Develop and maintain EDA tooling and flow automation (Tcl/Python/Make), build systems, and dashboards tracking release status and quality.
• Debug tooling and release failures end-to-end: analyze logs/reports, isolate root causes, and drive issues to closure with cross-functional teams.
• Apply AI tools to accelerate triage, summarize regression/QoR trends, and improve scripts and flows.
• Improve documentation, packaging criteria, and reusable collateral to ensure consistent, repeatable releases.
• Optional: contribute to mid-end logic flows (synthesis, DFT, STA, formal) where relevant to release readiness.

Requirements

Key must-have skills and practical experience for this role. Education details are listed separately below.

• Must-have: Working knowledge of EDA tooling and flow/automation development with demonstrated experience (~2+ years) or equivalent project work.
• Experience with product release and sign-off: packaging deliverables, running regressions, and verifying quality gates.
• Proficient scripting skills in Tcl and/or Python; automation-first mindset.
• Familiarity with build/packaging systems, revision control (Perforce or Git), and regression/CI flows.
• Practical understanding of ASIC design and verification flows sufficient to support and debug tooling.
• Ability to use AI tools effectively to speed debugging, summarize results, and improve scripts.
• Strong written and verbal communication; able to summarize issues, explain status/risks, and align cross-functional teams.
• Nice-to-have: hands-on logic engineering (synthesis, STA, DFT, static checking, formal equivalence, power analysis); experience with Synopsys tools (Fusion Compiler, VC SpyGlass, Formality); experience building CI/CD pipelines or dashboards.

Education Requirements

BS or MS in Electrical or Computer Engineering, Computer Science, or equivalent practical experience; equivalent project experience is acceptable.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.