EDA Flow and Logic Synthesis Engineer (Staff Engineer)

Job Title

EDA Flow and Logic Synthesis Engineer (Staff Engineer)

Role Summary

Work on mid-end flows for HPC Controller IP, converting RTL outputs into implementation-ready inputs and building automation to scale synthesis, DFT, static checking, formal equivalence, and power analysis. Collaborate with RTL designers, verification, DFT, physical design, methodology, and tooling teams to reduce implementation risk and improve handoffs.

This role emphasizes flow robustness, automation-first development (Tcl), and applying AI to accelerate debugging and improve engineering productivity.

Experience Level

Senior (Staff) — typically requires 5+ years of relevant ASIC/mid-end flow experience; title indicates a senior/staff-level role.

Responsibilities

Primary responsibilities focus on developing, supporting, and improving mid-end flows and ensuring clean handoffs to implementation teams.

• Develop, run, and support mid-end flows across synthesis, DFT, static checking, formal equivalence, and power analysis.
• Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design.
• Build and maintain Tcl-based automation, dashboards, and project infrastructure; apply AI to triage logs, summarize QoR trends, and draft/refactor scripts.
• Debug flow failures end-to-end: analyze reports, isolate root causes, and drive resolution with cross-functional teams.
• Improve documentation, handoff criteria, and reusable collateral to ensure consistent execution across IP programs.

Requirements

Core technical skills and experience required for successful performance in the role.

• Typically 5+ years of relevant ASIC design, verification, or mid-end flow experience or equivalent project work.
• Hands-on synthesis experience with ability to analyze and resolve synthesis issues.
• Strong Tcl scripting skills and an automation-first mindset.
• Familiarity with at least two of: DFT concepts, static checking (e.g., SpyGlass), formal equivalence (e.g., Formality), or power analysis, with willingness to expand across the rest.
• Practical experience using AI tools to accelerate debugging, summarize results, and improve scripts/flows.
• Strong analytical, problem-solving, communication, and documentation skills.

Nice to have:

• Experience across the full mid-end toolset (DFT, SpyGlass, Formality, power analysis).
• IP development methodologies, IP packaging, or reusable IP delivery/release collateral.
• Hands-on experience with Synopsys tools such as Fusion Compiler and VC SpyGlass.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or related technical field — or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.